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US4284854A
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Universal signal generator for generating telephone system high level signals
Assignee: Nortel Networks Ltd
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Filing: 1979-08-20
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Granted: 1981-08-18
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Expires: 1999-08-20
Abstract
Abstract In a telephone switching facility, line circuits are arranged in groups, each including a local ringing battery bus, and a universal high level signal generator (UHLSG) for providing ringing and other high level signals to the line circuits via the local ringing bus. Each generator is responsive to address signals from a controller in the switching facility to generate selected high level signals. The UHLSG includes a switching bridge driven by a width modulated signal stream of periodically occurring pulses having assertion times suitable for developing a high level signal across a network at the output of the switching bridge. The width modulated pulses are generated from period and time signals. The period signal occurs once with each sequence in repetitively generated data byte sequences. The time signal occurs with correspondence between a selected stored data byte and an instant one of the data bytes of the sequence. A plurality of the stored data bytes are arranged in ranges in a storage circuit. One bit in the last data byte in each range causes the storage circuit's next readout to be from the beginning of a range as directed by the controller in the switching facility.
Inventors
- 👤 Richard Hayward
- 👤 John Bottrill
- 👤 Robert C. Dittburner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:42
CPC Classifications
H; H04; H04M; H04M19/00; H04M19/02
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
161 words
A universal high level signal generator operable in response to clock signals, for generating selectable ones of a plurality of predetermined high level signals, comprising: storage means for storing a plurality of data bytes at least one of each relating to each of the predetermined high level signals; means for generating a signal stream of periodically occurring low and high signal states defining width modulated pulses in response to at least one of the data bytes from the storage means and the clock signals; a switching bridge having a control input connected to the signal stream generating means, a first pair of opposite terminals for connection to a source of energizing power, and a second pair of opposite terminals, the switching bridge being responsive to the high and low signal states of the signal stream, to alternately connect a potential, appearing across the first pair of opposite terminals, to the second pair of opposite terminals to provide said high level signals.
Claim 2
Dependent Claim
161 words
A universal high level signal generator operable in response to clock signals, for generating selectable ones of a plurality of predetermined high level signals, comprising: storage means for storing a plurality of data bytes at least one of each relating to each of the predetermined high level signals; means for generating a signal stream of periodically occurring low and high signal states defining width modulated pulses in response to at least one of the data bytes from the storage means and the clock signals; a switching bridge having a control input connected to the signal stream generating means, a first pair of opposite terminals for connection to a source of energizing power, and a second pair of opposite terminals, the switching bridge being responsive to the high and low signal states of the signal stream, to alternately connect a potential, appearing across the first pair of opposite terminals, to the second pair of opposite terminals to provide said high level signals.
Claim 3
Dependent Claim
68 words
A universal high level signal generator as defined in claim 1 further comprising a network including capacitive and inductive reactance elements, the network being connected across said second pair of opposite terminals, and an impulse filter connected in series with one of said first pair of opposite terminals, whereby the power signal is generated with reduced harmonic frequency content across one of the reactance elements of the network.
Claim 4
Dependent Claim
170 words
A universal high level signal generator as defined in claim 1 wherein the first pair of opposite terminals are positive and negative terminals and wherein the switching bridge comprises: a network having a reactive component; output terminals connected across the reactive component; a first set of two switches connected to the negative and positive power terminals respectively, and connected via said second pair of opposite terminals to opposite ends of and in series with the network, for applying voltage in one direction through the network in response to one of the signal states of the signal stream; a second set of two switches connected to the positive and negative power terminals respectively and connected via said second pair of opposite terminals at opposite ends and in series with the network, for applying voltage in the said other direction through the network in response to the other of the signal states of the signal stream; and an impulse filter connected in series with one of the positive or negative power terminals.
Claim 5
Dependent Claim
63 words
A universal high level signal generator as defined in claims 2 or 3 wherein the pulse repetition frequency of the signal stream produced by the generating means is a whole number multiple of at least twice the rate of occurrence of said data bytes from the storage means, whereby the required minimal value of the reactance component in the network is correspondingly reduced.
Claim 6
Dependent Claim
164 words
A universal high level signal generator as defined in claim 1 wherein the stoage means comprises: a memory having data bytes stored in ranges of address accessible locations, the data byte at each address corresponding to the conclusion of a range having a predetermined data bit of one state and the remaining data bytes of that range each having said predetermined data bit of the other state; a counter response to data input signals and a load signal for generating signals corresponding to addresses in said ranges to cause the memory to read out the associated data bytes, the counter being operable to continuously count from a starting point, the starting point being determined by the signal states of the data inputs at the moment of a signal assertion at the load input; and means connected between the memory and the load input for causing the signal assertion at the load input with the occurrence of said predetermined data bit of the one state.
Claim 7
Dependent Claim
214 words
A universal high level signal generator as defined in claim 1 wherein the switching bridge further comprises: a first set of two transistor switch circuits connected between the first and second pairs of terminals for applying voltage to the second pair of terminals in one direction; a second set of two transistor switch circuits connected between the first and second pairs of terminals for applying voltage to the second pair of terminals in the other direction; first and second primary windings and first and second pairs of secondary windings in respective first and second coupling transformers, the first pair of secondary windings connected to respective ones of the first set of the transistor switches, the second pair of secondary windings connected to respective ones of the second set of the transistor switches; first drive means connected to the first primary winding to periodically conduct current therethrough in response to the signal stream; second drive means connected to the second primary winding to periodically conduct current therethrough in inverse response to the signal stream; said secondary windings in said coupling transformers being poled to each supply turn ON current in the absence of current in the associated primary winding and to supply turn OFF bias in the presence of current in the associated primary winding.
Claim 8
Dependent Claim
32 words
A switching bridge as defined in claim 6 wherein each drive means includes a MOSFET device having a drain electrode connected in series with the respective primary winding for conducting said current.
References Cited (Backward Citations)
US4152670A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-08-17 | 1985-02-16 | 1985-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-08-17 | 1989-02-16 | 1989-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-08-17 | 1993-02-16 | 1993-08-18 | $7700.00 | Window Closed / Lapsed |