Patent US4283793A successfully refreshed from Google Patents.
US4283793A
Expired / Lapsed
US
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Muting signal generation circuit for an FM receiver
Assignee: Pioneer Corp
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Filing: 1979-10-02
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Granted: 1981-08-11
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Expires: 1999-10-02
Abstract
Abstract An improved muting signal generation circuit of an FM receiver of the type in which the deviation of an FM detection signal relative to a predetermined level is detected. When the deviation of the FM detected signal is above or below a predetermined value, a muting signal is generated. A band elimination filter is provided for eliminating the frequency components of an information signal contained in the FM detection signal. A detuning detection circuit detects detuning in response to the output of the band elimination filter. A muting signal generation circuit generates a muting signal in response to the detection output of the detuning detection circuit.
Inventors
- 👤 Tatsuo Numata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:05
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/34
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
91 words
In an FM receiver of the type having an FM detector, a muting circuit comprising: a band elimination filter means connected to said FM detector for eliminating the information content of the output of said FM detector and passing to an output thereof high frequency noise and the d.c. component in the FM detector output, and circuit means connected to the output of said band elmination filter means for generating a muting output signal in response to either one of said d.c. component and said noise being above a predetermined level.
Claim 2
Dependent Claim
91 words
In an FM receiver of the type having an FM detector, a muting circuit comprising: a band elimination filter means connected to said FM detector for eliminating the information content of the output of said FM detector and passing to an output thereof high frequency noise and the d.c. component in the FM detector output, and circuit means connected to the output of said band elmination filter means for generating a muting output signal in response to either one of said d.c. component and said noise being above a predetermined level.
Claim 3
Dependent Claim
42 words
The muting circuit of claim 1 wherein said muting signal generating means comprises: means for detecting variations in said detected FM signal beyond preset levels; and means for detecting the presence of noise components having a magnitude greater than a predetermined magnitude.
Claim 4
Dependent Claim
21 words
The muting circuit of claim 2 further comprising means for producing a muting signal in response to both said detecting means.
Claim 5
Dependent Claim
27 words
The muting circuit of claim 3 further comprising means coupled to said muting signal producing means for providing said muting signal with predetermined rise and fall times.
Claim 6
Dependent Claim
75 words
A muting circuit for an FM receiver comprising: band elimination filter means, an input of said band elimination filter means being coupled to a source of a detected FM signal; a complementary input circuit having an input coupled to an output of said band elimination filter means; first and second current mirror circuits coupled to said complementary input circuit; and an amplifier circuit coupled to respond to both said first and second current mirror circuits.
Claim 7
Dependent Claim
75 words
A muting circuit for an FM receiver comprising: band elimination filter means, an input of said band elimination filter means being coupled to a source of a detected FM signal; a complementary input circuit having an input coupled to an output of said band elimination filter means; first and second current mirror circuits coupled to said complementary input circuit; and an amplifier circuit coupled to respond to both said first and second current mirror circuits.
Claim 8
Dependent Claim
15 words
The muting circuit of claim 5 wherein said amplifier circuit comprises an emitter follower circuit.
Claim 9
Dependent Claim
19 words
The muting circuit of claim 6 further comprising a capacitor coupled to an output of said emitter follower circuit.
Claim 10
Dependent Claim
290 words
A muting circuit for an FM receiver comprising in combination: A. band elimination filter means, an input of said band elimination filter means being coupled to a source of a detected FM signal; and B. a combination detecting circuit, said combination detecting circuit comprising: (1) a complementary input circuit including a first NPN transistor and a first PNP transistor, said first NPN and said first PNP transistors having bases coupled to an output of said band elimination filter means and having emitters coupled to a source of a reference potential; (2) a first current mirror circuit including second and third PNP transistors, said second PNP transistor having a collector and a base coupled to the collector of said first NPN transistor and the base of said third PNP transistor and the emitter of said second PNP transistor being coupled to the emitter of said third PNP transistor and to a positive terminal of a power source; (3) a second current mirror circuit including second and third NPN transistors, said second NPN transistor having a collector and base coupled to the collector of said first PNP transistor and to the base of said third NPN transistor, the emitters of said second and third NPN transistors being coupled to a ground of said power source, and the collector of said third NPN transistor being coupled to the collector of said first NPN transistor; (4) an emitter follower circuit including a fourth NPN transistor having a base coupled to the collector of said third PNP transistor and one terminal of a first resistor, the second terminal of which is connected to ground, a collector coupled through a second resistor to said positive terminal and an emitter coupled through a third resistor to ground.
Claim 11
Dependent Claim
290 words
A muting circuit for an FM receiver comprising in combination: A. band elimination filter means, an input of said band elimination filter means being coupled to a source of a detected FM signal; and B. a combination detecting circuit, said combination detecting circuit comprising: (1) a complementary input circuit including a first NPN transistor and a first PNP transistor, said first NPN and said first PNP transistors having bases coupled to an output of said band elimination filter means and having emitters coupled to a source of a reference potential; (2) a first current mirror circuit including second and third PNP transistors, said second PNP transistor having a collector and a base coupled to the collector of said first NPN transistor and the base of said third PNP transistor and the emitter of said second PNP transistor being coupled to the emitter of said third PNP transistor and to a positive terminal of a power source; (3) a second current mirror circuit including second and third NPN transistors, said second NPN transistor having a collector and base coupled to the collector of said first PNP transistor and to the base of said third NPN transistor, the emitters of said second and third NPN transistors being coupled to a ground of said power source, and the collector of said third NPN transistor being coupled to the collector of said first NPN transistor; (4) an emitter follower circuit including a fourth NPN transistor having a base coupled to the collector of said third PNP transistor and one terminal of a first resistor, the second terminal of which is connected to ground, a collector coupled through a second resistor to said positive terminal and an emitter coupled through a third resistor to ground.
Claim 12
Dependent Claim
19 words
The muting circuit of claim 8 further comprising a capacitor coupled to the emitter of said fourth NPN transistor.
Claim 13
Dependent Claim
94 words
The muting circuit of claim 9 wherein said band elimination filter means comprises: fourth, fifth and sixth resistors coupled in series between said source of said detected FM signal and the bases of said first NPN and PNP transistors; a second capacitor coupled between the junction of said fourth and fifth resistors and ground; third and fourth capacitors coupled in series between opposite end terminals of said fourth and fifth resistors; and a seventh resistor coupled between said junction of said fourth and fifth resistors and the junction between said third and fourth capacitors.
References Cited (Backward Citations)
US2959673A
Cited
US3889192A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-08-10 | 1985-02-09 | 1985-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-08-10 | 1989-02-09 | 1989-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-08-10 | 1993-02-09 | 1993-08-11 | $7700.00 | Window Closed / Lapsed |