Line scan circuits for cathode ray tube displays

Claim 2

A line scan circuit for a cathode ray tube display adapted to receive horizontal synchronization pulses and to produce a line scan waveform comprising a phase detector adapted to compare the phase difference between said synchronization pulses and line flyback pulses and to produce an output representing the phase difference, an integrator adapted to integrate the output of the phase detector and having its output connected to a voltage controlled oscillator, and a line output stage connected to receive the output of said oscillator to produce said flyback pulses, characterized in that said phase detector is adapted to compare the phases of said synchronization and flyback pulses on both the leading and trailing edges thereof, and to produce phase difference signals therefrom which cause said flyback pulses to be centered on said synchronization pulses.

Claim 3

A line scan circuit as claimed in claim 1, characterized in that said phase detector includes a pulse shaping circuit adapted to receive said flyback pulses and to produce therefrom square-shaped flyback pulses whose leading and trailing edges coincide with those of the flyback pulses and a distinguishing signal that changes state in accordance with the peaks of the flyback pulses, in that said square-shaped pulses are used as timing reference signals, and in that said distinguishing signal is used to distinguish between the leading and trailing edges of said square-shaped pulses.

Claim 4

A line scan circuit as claimed in claim 2, characterized in that said distinguishing signal and said square-shaped pulses are each produced by a Schmitt trigger.

Claim 5

A line scan circuit as claimed in claim 2 or claim 3, characterized in that said phase detector includes digital logical circuits adapted to combine the synchronization and square-shaped pulses with said distinguishing signal to produce a first-type signal indicative of the phase difference between the leading edges of the synchronization and square-shaped pulses and a second-type signal indicative of the phase difference between the trailing edges of the synchronization and square-shaped pulses.

Claim 6

A line scan circuit as claimed in claim 4, characterized in that said first-type and second-type signals are produced respectively from the outputs of the first and second OR gates connected to receive respectively the outputs of first and second parts of AND gates, in that one of said first pair or AND gates is connected to give an output in the presence of a synchronizing pulse and the absence of a square-shaped pulse and said distinguishing signal and in that the other of said first pair of AND gates is connected to give an output in the absence of a synchronization pulse and the presence of a square-shaped pulse and said distinguishing signal, and in that one of the second pair of AND gates is connected to give an output in the presence of a synchronization pulse and said distinguishing signal and the absence of a square-shaped pulse and in that the other of said second pair of AND gates is connected to give an output in the absence of a synchronization pulse and said distinguishing signal and the presence of a square-shaped pulse.

Claim 7

A line scan circuit as claimed in claim 5, characterized in that said first pair of AND gates are connected to receive delayed synchronization pulses.