Circuit for reducing the loading effect of an insulated-gate field-effect transistor (IGFET) on a signal source

Claim 2

In combination with an insulated-gate field-effect transistor (IGFET) having source and drain regions spaced apart by a substrate region, and wherein said source region forms a first rectifying junction with said substrate region and said drain region forms a second rectifying junction with said substrate region, said first and second junctions being poled to conduct current in opposite direction and wherein said substrate region is electrically floating, the improvement comprising: means for first applying to said source region a signal making a first transition from a first voltage (V 1 ) to a second voltage (V 2 ) of a polarity and magnitude to forward bias said source-to-substrate junction for placing said substrate region at a potential close to said second voltage and for then applying a signal making a second transition of a polarity opposite to said first transition for reverse biasing said source-to-substrate junction and isolating said substrate region from said source region.

Claim 3

In the combination as claimed in claim 1 wherein said second transition of said signal goes from said second voltage (V 2 ) to a third voltage (V 3 ), where V 3 is intermediate said first and second voltages; and wherein said improvement further comprises means for turning off said IGFET during the application of said signal.

Claim 4

In the combination as claimed in claim 1 wherein said potential close to said second voltage defines a first level (L 1 ) which is equal to V 2 -V F , where V F is the forward voltage drop of said source-to-substrate region.

Claim 5

In the combination as claimed in claim 3, wherein in response to said second transition said substrate potential changes in value from said first level (V 2 -V F ) to a second level intermediate the first level and V 3 ; and wherein said source-to-substrate junction remains reverse biased for all values of signal subsequently applied to said source region ranging in value between said first voltage to said second level L 2 .

Claim 6

In the combination as claimed in claim 1 wherein said IGFET is formed on an insulator layer; and wherein said IGFET includes a gate electrode isolated from and overyling said substrate region.

Claim 7

The combination comprising: a storage element having an input-output (I/O) point to which is applied data to be stored and from which is extracted data to be sensed; an insulated-gate field-effect transistor (IGFET) having source and drain regions separated by a substrate region, said source and drain regions forming respective junctions with said substrate poled to conduct in opposite directions and said substrate being electrically floating; said IGFET having a control electrode overlying said substrate region for the application thereto of turn-on and turn-off voltages; a bit line; means directly connecting one of said source and drain regions to said input/output point; and the other one of said source and drain regions to said bit line; precharge means coupled to said bit line for selectively applying thereto a precharge pulse making a first transition between a first voltage and a second voltage of a polarity to forward bias said source-to-substrate region and placing said substrate region at a potential level close to said second voltage and said precharge pulse making a subsequent transition of opposite polarity to said first transition; and means coupled to said control electrode for applying a turn-off voltage to said control electrode during the application of said precharge pulse.

Claim 8

The combination comprising: a storage element having an input-output (I/O) point to which is applied data to be stored and from which is extracted data to be sensed; an insulated-gate field-effect transistor (IGFET) having source and drain regions separated by a substrate region, said source and drain regions forming respective junctions with said substrate poled to conduct in opposite directions and said substrate being electrically floating; said IGFET having a control electrode overlying said substrate region for the application thereto of turn-on and turn-off voltages; a bit line; means directly connecting one of said source and drain regions to said input/output point; and the other one of said source and drain regions to said bit line; precharge means coupled to said bit line for selectively applying thereto a precharge pulse making a first transition between a first voltage and a second voltage of a polarity to forward bias said source-to-substrate region and placing said substrate region at a potential level close to said second voltage and said precharge pulse making a subsequent transition of opposite polarity to said first transition; and means coupled to said control electrode for applying a turn-off voltage to said control electrode during the application of said precharge pulse.

Claim 9

The combination as claimed in claim 6 wherein said source, drain and substrate regions of said IGFET are formed on a layer of insulating material.

Claim 10

The combination as claimed in claim 7 wherein said subsequent transition of opposite polarity goes from said second level to a third level intermediate said first and second levels; and wherein said source-to-substrate region is reverse biased when said signal makes a subsequent transition.

Claim 11

In a memory system which has a common bit line, a plurality of memory cells each connected to the bit line by a gating transistor where each gating transistor includes source, drain, and substrate regions and a gate electrode, with capacitance (C SB ) between the source and substrate regions, capacitance (C BD ) between the substrate and drain regions, capacitance (C BG ) between the substrate and gate electrode, a diode (D SB ) between the source and substrate regions, and a diode (D BD ) between the substrate and drain regions, and where when it is desired to read the contents of a memory cell its associated gating transistor is turned-on and all the other gating transistors are turned off and the time required for current from the selected cell to pass through the turned-on gating transistor to charge the bit line to a desired threshold level indicative of the value of the information stored in the selected cell is affected by the charge stored in the capacitances of the turned-off gating transistors, an improvement for reducing the effect of the capacitance of the non-selected cells on the read out time of the selected cell comprising: means for selectively turning off all the gating transistors; and means for then, prior to the turn-on of any one of said gating transistors, applying a precharge pulse to said common bit line of a polarity to forward bias the source-to-substrate region of all said gating transistors and placing the substrates at a predetermined level whereby the source-to-substrate junctions of all the turned-off gating transistors will be reverse biased for all signals applied to said common bit line having a polarity to forward bias said source-to-substrate region in a range extending to said predetermined level.

Claim 12

In a memory system which has a common bit line, a plurality of memory cells each connected to the bit line by a gating transistor where each gating transistor includes source, drain, and substrate regions and a gate electrode, with capacitance (C SB ) between the source and substrate regions, capacitance (C BD ) between the substrate and drain regions, capacitance (C BG ) between the substrate and gate electrode, a diode (D SB ) between the source and substrate regions, and a diode (D BD ) between the substrate and drain regions, and where when it is desired to read the contents of a memory cell its associated gating transistor is turned-on and all the other gating transistors are turned off and the time required for current from the selected cell to pass through the turned-on gating transistor to charge the bit line to a desired threshold level indicative of the value of the information stored in the selected cell is affected by the charge stored in the capacitances of the turned-off gating transistors, an improvement for reducing the effect of the capacitance of the non-selected cells on the read out time of the selected cell comprising: means for selectively turning off all the gating transistors; and means for then, prior to the turn-on of any one of said gating transistors, applying a precharge pulse to said common bit line of a polarity to forward bias the source-to-substrate region of all said gating transistors and placing the substrates at a predetermined level whereby the source-to-substrate junctions of all the turned-off gating transistors will be reverse biased for all signals applied to said common bit line having a polarity to forward bias said source-to-substrate region in a range extending to said predetermined level.