US4278943A
Expired / Lapsed
US
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Integration circuit
Assignee: Toshiba Corp
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Filing: 1978-06-29
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Granted: 1981-07-14
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Expires: 1998-06-29
Abstract
Abstract An integration circuit comprises an operational amplifier with first and second input terminals and an output terminal, an integration capacitor connected between the first input terminal and the output terminal, an integration resistor connected at one end to the first input terminal, a switch connected at one end to the other end of said resistor, a voltage signal source to be integrated which is connected through the switch to the other end of the resistor, and a reference voltage signal source connected to the second input terminal. The integration circuit further comprises means which applies, at the same time as the switch is opened, a signal with the same potential as the signal derived from the reference voltage signal source to said other end of the resistor, thereby to prevent an output signal from being adversely affected by a parasitic capacitance of the switch. An integration method includes a first step for applying a voltage signal to be integrated to an input part of an integration circuit and a second step for stopping the application of the integration voltage signal to the input part, and further comprises a third step for applying a reference potential signal to the input part of the integration circuit at the same time as the voltage signal to be integrated stops.
Inventors
- 👤 Eiji Masuda
- 👤 Chikara Sato
- 👤 Yasoji Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:41
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/18; G06G7/184; G06G7/186; G06G7/1865
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
144 words
An integration method using an integration circuit having operational amplifying means with first and second input terminals and an output terminal and receiving at said first input terminal a reference potential signal, capacitor means connected between said second input terminal and said output terminal of said amplifying means, and resistive means having first and second ends, said resistive means connected at said first end to said second input terminal of said amplifying means and said resistive means selectively connected at said second end to a voltage signal to be integrated, comprising a step of directly and non-resistively applying a signal with substantially the same potential as the potential of said reference potential signal to said second end of said resistive means, and at the same time stopping the application of said voltage signal to be integrated to said second end of the resistive means.
Claim 2
Dependent Claim
144 words
An integration method using an integration circuit having operational amplifying means with first and second input terminals and an output terminal and receiving at said first input terminal a reference potential signal, capacitor means connected between said second input terminal and said output terminal of said amplifying means, and resistive means having first and second ends, said resistive means connected at said first end to said second input terminal of said amplifying means and said resistive means selectively connected at said second end to a voltage signal to be integrated, comprising a step of directly and non-resistively applying a signal with substantially the same potential as the potential of said reference potential signal to said second end of said resistive means, and at the same time stopping the application of said voltage signal to be integrated to said second end of the resistive means.
Claim 3
Dependent Claim
154 words
An integration method using an integration circuit having operational amplifying means with first and second input terminals and an output terminal and receiving at said first input terminal a reference potential signal, capacitor means connected between said second input terminal and said output terminal of said amplifying means, and resistive means having first and second ends, said resistive means connected at said first end to said second input terminal of said amplifying means and said resistive means selectively connected at said second end to any one of a plurality of voltage signals to be integrated, comprising a step of directly and non-resistively applying a signal with substantially the same potential as the potential of said reference potential signal to said second end of said resistive means, and at the same time stopping the application of any one of said plurality of voltage signals to be integrated to said second end of said resistive means.
Claim 4
Dependent Claim
154 words
An integration method using an integration circuit having operational amplifying means with first and second input terminals and an output terminal and receiving at said first input terminal a reference potential signal, capacitor means connected between said second input terminal and said output terminal of said amplifying means, and resistive means having first and second ends, said resistive means connected at said first end to said second input terminal of said amplifying means and said resistive means selectively connected at said second end to any one of a plurality of voltage signals to be integrated, comprising a step of directly and non-resistively applying a signal with substantially the same potential as the potential of said reference potential signal to said second end of said resistive means, and at the same time stopping the application of any one of said plurality of voltage signals to be integrated to said second end of said resistive means.
Claim 5
Dependent Claim
171 words
An integration method using an integration circuit having operational amplifying means with first and second input terminals and an output terminal and receiving at said first input terminal a reference potential signal, capacitor means connected between said second input terminal and said output terminal, and resistive means having first and second ends, said resistive means connected at said first end to said second input terminal, comprising a step (A) of applying a voltage signal to be integrated to said second end of said resistive means, while at the same time preventing application of a signal having substantially the same potential as the potential of said reference potential signal to said second end of the resistive means, and a step (B) of stopping the application of said voltage signal to be integrated to said second end of the resistive means, and at the same time directly and non-resistively applying said signal having substantially the same potential as the potential of said reference potential signal to said second end of said resistive means.
Claim 6
Dependent Claim
171 words
An integration method using an integration circuit having operational amplifying means with first and second input terminals and an output terminal and receiving at said first input terminal a reference potential signal, capacitor means connected between said second input terminal and said output terminal, and resistive means having first and second ends, said resistive means connected at said first end to said second input terminal, comprising a step (A) of applying a voltage signal to be integrated to said second end of said resistive means, while at the same time preventing application of a signal having substantially the same potential as the potential of said reference potential signal to said second end of the resistive means, and a step (B) of stopping the application of said voltage signal to be integrated to said second end of the resistive means, and at the same time directly and non-resistively applying said signal having substantially the same potential as the potential of said reference potential signal to said second end of said resistive means.
Claim 7
Dependent Claim
15 words
An integration method according to claim 3, wherein said steps (A) and (B) are repeated.
Claim 8
Dependent Claim
177 words
An integration method using an integration circuit having operational amplifying means with first and second input terminals and an output terminal and receiving at said first input terminal a reference potential signal, capacitor means connected between said second input terminal and said output terminal, and resistive means having first and second ends, said resistive means connected at said first end to said second input terminal, comprising a step (A) of applying any one of a plurality of voltage signals to be integrated to said second end of said resistive means, while at the same time preventing application of a signal having substantially the same potential as the potential of said reference potential signal to said second end of said resistive means, and a step (B) of stopping the application of said one voltage signal to be integrated to said second end of said resistive means, and at the same time directly and non-resistively applying said signal having substantially the same potential as the potential of said reference potential signal to said second end of said resistive means.
Claim 9
Dependent Claim
177 words
An integration method using an integration circuit having operational amplifying means with first and second input terminals and an output terminal and receiving at said first input terminal a reference potential signal, capacitor means connected between said second input terminal and said output terminal, and resistive means having first and second ends, said resistive means connected at said first end to said second input terminal, comprising a step (A) of applying any one of a plurality of voltage signals to be integrated to said second end of said resistive means, while at the same time preventing application of a signal having substantially the same potential as the potential of said reference potential signal to said second end of said resistive means, and a step (B) of stopping the application of said one voltage signal to be integrated to said second end of said resistive means, and at the same time directly and non-resistively applying said signal having substantially the same potential as the potential of said reference potential signal to said second end of said resistive means.
Claim 10
Dependent Claim
27 words
An integration method according to claim 5, wherein said steps (A) and (B) are carried out for each of said plurality of voltage signals to be integrated.
Claim 11
Dependent Claim
211 words
An integration circuit comprising operational amplifying means with first and second input terminals and an output terminal and receiving at said first input terminal a reference potential signal, capacitor means connected between said second input terminal and said output terminal of said amplifying means, resistive means having first and second ends, said resistive means connected at said first end to said second input terminal of said amplifying means, a voltage signal source for generating a voltage signal to be integrated; first switch means connected between said second end of said resistive means and said voltage signal source; a control signal source for generating a control signal to control the opening and closing of said first switch means; a reference voltage signal source connected to said first input terminal of the operational amplifying means to generate said reference potential signal; and second switch means connected to said second end of said resistive means to directly and non-resistively apply a signal with substantially the same potential as the potential of said reference potential signal to said second end of said resistive means, when said first switch means is opened to stop the supply of said voltage signal to be integrated from said voltage signal source to said second end of said resistive means.
Claim 12
Dependent Claim
211 words
An integration circuit comprising operational amplifying means with first and second input terminals and an output terminal and receiving at said first input terminal a reference potential signal, capacitor means connected between said second input terminal and said output terminal of said amplifying means, resistive means having first and second ends, said resistive means connected at said first end to said second input terminal of said amplifying means, a voltage signal source for generating a voltage signal to be integrated; first switch means connected between said second end of said resistive means and said voltage signal source; a control signal source for generating a control signal to control the opening and closing of said first switch means; a reference voltage signal source connected to said first input terminal of the operational amplifying means to generate said reference potential signal; and second switch means connected to said second end of said resistive means to directly and non-resistively apply a signal with substantially the same potential as the potential of said reference potential signal to said second end of said resistive means, when said first switch means is opened to stop the supply of said voltage signal to be integrated from said voltage signal source to said second end of said resistive means.
Claim 13
Dependent Claim
17 words
An integration circuit according to claim 7, in which said first switch means is a bipolar transistor.
Claim 14
Dependent Claim
17 words
An integration circuit according to claim 7, in which said first switch means is a unipolar transistor.
Claim 15
Dependent Claim
63 words
An integration circuit according to claim 7, in which said first switch means comprises: inverter means for inverting the phase of said control signal from said control signal source; and a switch connected between said second end of said resistor and said reference voltage signal source, the opening and closing of said switch being controlled by the output signal from said inverter means.
Claim 16
Dependent Claim
15 words
An integration circuit according to claim 10, in which said switch is a bipolar transistor.
Claim 17
Dependent Claim
15 words
An integration circuit according to claim 10, in which said switch is a unipolar transistor.
Claim 18
Dependent Claim
224 words
An integration circuit comprising operational amplifying means with first and second input terminals and an output terminal and receiving at said first input terminal a reference potential signal, capacitor means connected between said second input terminal and said output terminal of said amplifying means, and resistive means having first and second ends, said resistive means connected at said first end to said second input terminal of said amplifying means, a plurality of voltage signal sources for generating voltage signals to be integrated; a plurality of first switch means connected in parallel between said second end of said resistive means and said voltage signal sources; a plurality of control signal sources each correspondingly provided for said first switch means to control the opening and closing of a corresponding first switch means; a reference voltage signal source connected to said first input terminal of said operational amplifying means to generate said reference potential signal; and second switch means connected to said second end of said resistive means to directly and non-resistively apply a signal with substantially the same potential as the potential of said reference potential signal to said second end of said resistive means when said first switch means are opened to stop the supply of said voltage signals to be integrated to said second end of said resistive means from said voltage signal sources.
Claim 19
Dependent Claim
224 words
An integration circuit comprising operational amplifying means with first and second input terminals and an output terminal and receiving at said first input terminal a reference potential signal, capacitor means connected between said second input terminal and said output terminal of said amplifying means, and resistive means having first and second ends, said resistive means connected at said first end to said second input terminal of said amplifying means, a plurality of voltage signal sources for generating voltage signals to be integrated; a plurality of first switch means connected in parallel between said second end of said resistive means and said voltage signal sources; a plurality of control signal sources each correspondingly provided for said first switch means to control the opening and closing of a corresponding first switch means; a reference voltage signal source connected to said first input terminal of said operational amplifying means to generate said reference potential signal; and second switch means connected to said second end of said resistive means to directly and non-resistively apply a signal with substantially the same potential as the potential of said reference potential signal to said second end of said resistive means when said first switch means are opened to stop the supply of said voltage signals to be integrated to said second end of said resistive means from said voltage signal sources.
Claim 20
Dependent Claim
16 words
An integration circuit according to claim 13, in which said first switch means comprise bipolar transistors.
Claim 21
Dependent Claim
16 words
An integration circuit according to claim 13, in which said first switch means comprise unipolar transistors.
Claim 22
Dependent Claim
74 words
An integration circuit according to claim 13, in which said second switch means comprises: a detecting circuit which detects a non-active state of the control signal from each of said control signal sources to produce an active state signal; and a switch connected between said second end of said resistive means and said reference voltage signal source, opening and closing of said switch being controlled by said active state signal from said detecting circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-07-13 | 1985-01-12 | 1985-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-07-13 | 1989-01-12 | 1989-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-07-13 | 1993-01-12 | 1993-07-14 | $7700.00 | Window Closed / Lapsed |