Semiconductor circuit for voltage conversion

Claim 2

A semiconductor voltage converter circuit including a capacitor (C 1 ) having a pair of terminals each of which is connected through the source-drain path of a separate MOS transistor switch (M 3 , M 5 ) to a separate first and second voltage source terminal (ground, V 1 ), for alternately connecting the disconnecting said capacitor (C 1 ) to said first and second voltage source terminals (ground, V 1 ), one of said terminals of the capacitor (C 1 ) being also connected through the source-drain path of a series-connected MOS transistor (M 1 ) to a third input voltage source terminal (V 2 ), the other of said terminals of the capacitor (C 1 ) being connected to an output node (13), the gate electrode of said series-connected transistor (M 1 ) being connected to another MOS transistor switch (M 4 ) for alternately turning "on" and "off" said series-connected transistor (M 1 ), characterized in that said circuit further includes a feedback loop running from the other terminal of said capacitor (C 1 ) through a load (M 2 ) back to the gate electrode of said series connected MOS transistor (M 1 ).

Claim 3

A circuit in accordance with claim 1 further characterized in that said load (M 2 ) is the source-drain path of an MOS transistor (M 2 ) whose gate electrode is connected through the source-drain path of yet another MOS transistor (M 6 ) to a voltage source terminal and to one terminal of a second, smaller capacitor (C 2 ) having another terminal which is connected to the gate electrode of the series-connected transistor (M 1 ).

Claim 4

A circuit according to claim 2 which further includes a bootstrap capacitor (C 3 ) one of whose terminals is connected to the gate electrode of both the MOS transistors M 5 and M 6 and the other of whose terminals is connected to a pulsed voltage source terminal (17).

Claim 5

A circuit according to claim 3 in which the gate electrodes of both the MOS transistors M 5 and M 6 are connected to one of the high current carrying terminals of each of two additional MOS transistors (M 7 and M 8 ), the gate electrode of M 8 being connected to the gate electrodes of M 5 and M 6 , the gate electrode of M 7 being connected to the other of the high current carrying terminals of M 8 and to the voltage source terminal V 1 .

Claim 6

Semiconductor apparatus comprising: (a) a first capacitor having first and second terminals, the second terminal being connected to an output node; (b) a first transistor having a pair of high current terminals and a low current control terminal, one of said high current terminals connected to the first terminal of the first capacitor and the other of said high current terminals connected to an input voltage terminal, said control terminal connected through a load device to the second terminal of the first capacitor; (c) first means, connected to said control terminal and said one of said high current terminals, for alternately turning "off" and "on" said first transistor; (d) second means, connected to the second terminal of said first capacitor, for alternately connecting and disconnecting said second terminal of the first capacitor to and from a first voltage supply terminal.

Claim 7

Semiconductor apparatus comprising: (a) a first capacitor having first and second terminals, the second terminal being connected to an output node; (b) a first transistor having a pair of high current terminals and a low current control terminal, one of said high current terminals connected to the first terminal of the first capacitor and the other of said high current terminals connected to an input voltage terminal, said control terminal connected through a load device to the second terminal of the first capacitor; (c) first means, connected to said control terminal and said one of said high current terminals, for alternately turning "off" and "on" said first transistor; (d) second means, connected to the second terminal of said first capacitor, for alternately connecting and disconnecting said second terminal of the first capacitor to and from a first voltage supply terminal.

Claim 8

Apparatus according to claim 5 in which the first capacitor is an MOS capacitor, the first transistor is an MOS transistor, and the load device is a second MOS transistor whose gate electrode is connected to its source through a second MOS capacitor.

Claim 9

Apparatus according to claim 6 in which the gate electrode of the second MOS transistor is connected to third means for alternately connecting and disconnecting said gate electrode of said second transistor to and from said first voltage supply terminal.

Claim 10

Apparatus according to claim 6 or 7 in which said first means comprise third and fourth MOS transistors, the drain of said third transistor being connected to said one of the high current carrying terminals of said first transistor, the drain of said fourth transistor being connected to the gate electrode of the first transistor and the gate electrodes of said third and fourth transistor being connected to means for alternately turning "off" and "on" said third and fourth transistors.

Claim 11

Apparatus according to claim 8 in which said second and third means comprise, respectively, fifth and sixth MOS transistors whose gate electrode are connected to an additional means for alternately turning "off" and "on" said fifth and sixth transistors, the sources of said fifth and sixth transistors being connected, respectively, to the second terminal of the first capacitor and the gate electrode of the second transistor.

Claim 12

Apparatus according to claim 9 which further includes a seventh MOS transistor and a third capacitor, the gate electrode of said seventh transistor being connected to its drain, the drain of the seventh transistor being conncted to the drain of the fifth transistor, the source of the seventh transistor being connected to one terminal of the third capacitor, the other terminal of the third capacitor being connected both to the gate electrode of the third transistor and to a pulsed voltage source terminal.

Claim 13

Apparatus according to claim 10 which further includes an eighth MOS transistor whose drain is connected to the drain of the seventh transistor and whose source and gate electrode are both connected to said one terminal of the third capacitor.

Claim 14

Apparatus according to claim 6 in which the capacitance of the first capacitor is larger than that of the second capacitor.

Claim 15

A voltage converter circuit stage comprising: (a) a first MOS transistor, one of whose high current carrying terminals is connected to a first node, another of whose high current carrying terminals is connected to a stage input terminal, and whose low current carrying terminal is connected to a second node; (b) a first capacitor having one of its terminals connected to said first node and another of its terminals connected to a stage output terminal; (c) a second smaller capacitor having one of its terminals connected to said second node and another of its terminals connected to a third node; (d) a second MOS transistor, one of whose high current terminals is connected to said second node, another of whose high current terminals is connected to said output terminal, and whose low current terminal is connected to said third node; and (e) first, second, third, and fourth switching means for alternately connecting and disconnecting respectively, said first node to and from a first reference potential terminal, said second node to and from said first reference potential terminal, said third node to and from a second reference potential terminal, said output node to and from said second reference potential terminal.

Claim 16

A voltage converter circuit stage comprising: (a) a first MOS transistor, one of whose high current carrying terminals is connected to a first node, another of whose high current carrying terminals is connected to a stage input terminal, and whose low current carrying terminal is connected to a second node; (b) a first capacitor having one of its terminals connected to said first node and another of its terminals connected to a stage output terminal; (c) a second smaller capacitor having one of its terminals connected to said second node and another of its terminals connected to a third node; (d) a second MOS transistor, one of whose high current terminals is connected to said second node, another of whose high current terminals is connected to said output terminal, and whose low current terminal is connected to said third node; and (e) first, second, third, and fourth switching means for alternately connecting and disconnecting respectively, said first node to and from a first reference potential terminal, said second node to and from said first reference potential terminal, said third node to and from a second reference potential terminal, said output node to and from said second reference potential terminal.

Claim 17

A voltage converter semiconductor circuit comprising: (a) a plurality of successive stages each in accordance with the circuit stage recited in claim 13, the stage input terminal of each stage, except the first, being connected to the stage output terminal of the immediately preceding stage; and (b) an output MOS transistor, whose gate electrode is connected to the gate electrode of said second transistor of the last stage, one of whose high current carrying terminals is connected to the output terminal of the last stage and another of whose high current terminals is connected to a utilization meams terminal.

Claim 18

A voltage multiplier semiconductor circuit stage comprising: (a) an input terminal; (b) a first MOS transistor, one of whose high current carrying terminals is connected to said input terminal; (c) a first MOS capacitor, one of whose terminals is connected to another high current carrying terminal of the first transistor; (d) an output terminal to which is connected another terminal of the first capacitor; (e) an MOS load device, one of its terminals connected to said another terminal of the first capacitor and another of its terminals connected to the gate electrode of the first transistor; (f) first means for alternately connecting and disconnecting the gate electrode of said first transistor to and from a reference voltage terminal; (g) second means for alternately connecting and disconnecting said one terminal of the first capacitor to and from said reference voltage terminal; (h) third means for alternately connecting and disconnecting said another terminal of the first capacitor to a voltage supply terminal.

Claim 19

A voltage multiplier semiconductor circuit stage comprising: (a) an input terminal; (b) a first MOS transistor, one of whose high current carrying terminals is connected to said input terminal; (c) a first MOS capacitor, one of whose terminals is connected to another high current carrying terminal of the first transistor; (d) an output terminal to which is connected another terminal of the first capacitor; (e) an MOS load device, one of its terminals connected to said another terminal of the first capacitor and another of its terminals connected to the gate electrode of the first transistor; (f) first means for alternately connecting and disconnecting the gate electrode of said first transistor to and from a reference voltage terminal; (g) second means for alternately connecting and disconnecting said one terminal of the first capacitor to and from said reference voltage terminal; (h) third means for alternately connecting and disconnecting said another terminal of the first capacitor to a voltage supply terminal.

Claim 20

A circuit stage according to claim 15 in which said load device comprises a second MOS transistor, one of whose high current carrying terminals is connected to the output terminal and the other of whose high current terminals is connected to the gate electrode of the first transistor, and the said other high current terminal of the second transistor being connected to one terminal of a second capacitor, the gate electrode of said second transistor being connected both to another terminal of the second capacitor and to fourth means for alternately connecting and disconnecting said gate electrode of said second transistor to said voltage supply terminal.

Claim 21

A voltage multiplier semiconductor circuit comprising: (a) a plurality of successive stages each in accordance with claim 16; (b) stage interconnecting means for connecting the output terminal of each stage, except the last, to the input terminal of the immediately succeeding stage; (c) output means for alternately connecting and disconnecting the output terminal of the last stage to a utilization means terminal.

Claim 22

A circuit according to claim 17 in which said output means includes an output MOS transistor whose gate electrode is connected to the gate electrode of the second transistor of the last stage, one of the high current carrying terminals of the output transistor being connected to said utilization means terminal and another of the high current carrying terminals of the output transistor being connected to the output terminal of the last stage.