Patent US4275362A successfully refreshed from Google Patents.
US4275362A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gain controlled amplifier using a pin diode
Assignee: RCA Licensing Corp
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Filing: 1979-03-16
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Granted: 1981-06-23
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Expires: 1999-03-16
Abstract
Abstract A gain controlled amplifier is provided which is capable of handling a wide range of input signal levels without the need for input signal attenuation. A transistor is arranged in a common emitter amplifier configuration and includes a PIN diode as a controllable impedance in the emitter circuit. An input signal and a gain control voltage are applied at the base of the transistor. As the input signal level increases, the gain control voltage is decreased, causing an increase in the substantially resistive impedance of the PIN diode, which bears a constant relationship to the decreasing gain control voltage (i.e., a linear relationship on a semilog plot). The gain of the transistor amplifier is thereby reduced. At high input signal levels, the impedance of the PIN diode comprises a large resistive component in parallel with a large reactive (i.e., small capacitive) component at the emitter of the transistor, thereby affording substantial gain reduction. A novel PIN diode is provided for use in such a gain controlled amplifier, comprising a first localized region of high resistivity semiconductor material having a substantially planar surface. Second and third localized regions of one type conductivity are located in the high resistivity region adjacent to the surface. A fourth localized region of opposite type conductivity is located in the high resistivity region adjacent to the surface and intermediate the second and third localized regions, and is separated laterally from the first and second regions by zones of the high resistivity material.
Inventors
- 👤 Jack R. Harford
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:31
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/02; H03G3/04; H03G3/10; H03G1/00; H03G1/0005; H03G1/0035; H03G1/0052; H03G1/0058; H03G3/20; H03G3/30; H03G3/3052; H03G3/3057
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
83 words
A gain controlled amplifier comprising: a transistor including base, emitter, and collector electrodes, and coupled in a common emitter amplifier configuration; a source of input signals coupled to said base electrode; a load impedance coupled to said collector electrode; a PIN diode direct current coupled between said emitter electrode and a point of reference potential, and biased for forward conduction; and a source of gain control voltage coupled to said transistor for simultaneously varying the bias of said transistor and said PIN diode.
Claim 2
Dependent Claim
83 words
A gain controlled amplifier comprising: a transistor including base, emitter, and collector electrodes, and coupled in a common emitter amplifier configuration; a source of input signals coupled to said base electrode; a load impedance coupled to said collector electrode; a PIN diode direct current coupled between said emitter electrode and a point of reference potential, and biased for forward conduction; and a source of gain control voltage coupled to said transistor for simultaneously varying the bias of said transistor and said PIN diode.
Claim 3
Dependent Claim
119 words
A gain controlled amplifier comprising: a transistor including base, emitter, and collector electrodes, and coupled in a common emitter amplifier configuration; a source of input signals coupled to said base electrode; a load impedance coupled to said collector electrode; a PIN diode direct current coupled between said emitter electrode and a point of reference potential, and biased for forward conduction; a source of gain control voltage coupled to said transistor for simultaneously varying the bias of said transistor and said PIN diode; and a second transistor for coupling said load impedance to the collector electrode of said first transistor, said second transistor being arranged in a common base configuration, wherein said first and second transistors comprise a cascode amplifier.
Claim 4
Dependent Claim
119 words
A gain controlled amplifier comprising: a transistor including base, emitter, and collector electrodes, and coupled in a common emitter amplifier configuration; a source of input signals coupled to said base electrode; a load impedance coupled to said collector electrode; a PIN diode direct current coupled between said emitter electrode and a point of reference potential, and biased for forward conduction; a source of gain control voltage coupled to said transistor for simultaneously varying the bias of said transistor and said PIN diode; and a second transistor for coupling said load impedance to the collector electrode of said first transistor, said second transistor being arranged in a common base configuration, wherein said first and second transistors comprise a cascode amplifier.
Claim 5
Dependent Claim
139 words
A gain controlled amplifier comprising: a transistor including base, emitter, and collector electrodes, and coupled in a common emitter amplifier configuration; a source of input signals coupled to said base electrode; a load impedance coupled to said collector electrode; a PIN diode direct current coupled between said emitter electrode and a point of reference potential, and biased for forward conduction; a source of gain control voltage coupled to said transistor for simultaneously varying the bias of said transistor and said PIN diode; and a second transistor for coupling said load impedance to the collector electrode of said first transistor, said second transistor being arranged in a common base configuration, wherein said first and second transistors comprise a cascode amplifier, and wherein said first and second transistors, and said PIN diode are located on a single monolithic integrated circuit chip.
Claim 6
Dependent Claim
139 words
A gain controlled amplifier comprising: a transistor including base, emitter, and collector electrodes, and coupled in a common emitter amplifier configuration; a source of input signals coupled to said base electrode; a load impedance coupled to said collector electrode; a PIN diode direct current coupled between said emitter electrode and a point of reference potential, and biased for forward conduction; a source of gain control voltage coupled to said transistor for simultaneously varying the bias of said transistor and said PIN diode; and a second transistor for coupling said load impedance to the collector electrode of said first transistor, said second transistor being arranged in a common base configuration, wherein said first and second transistors comprise a cascode amplifier, and wherein said first and second transistors, and said PIN diode are located on a single monolithic integrated circuit chip.
Claim 7
Dependent Claim
83 words
A gain controlled amplifier comprising: a transistor including base, emitter and collector electrodes and a forward biased base-to-emitter junction; a source of input signals coupled to said base electrode; a load impedance coupled to said collector electrode; a PIN diode direct current coupled between said emitter electrode and a point of reference potential and biased for forward conduction; and a source of variable gain control voltage coupled to said transistor for simultaneously controlling the forward bias of said transistor and said PIN diode.
Claim 8
Dependent Claim
83 words
A gain controlled amplifier comprising: a transistor including base, emitter and collector electrodes and a forward biased base-to-emitter junction; a source of input signals coupled to said base electrode; a load impedance coupled to said collector electrode; a PIN diode direct current coupled between said emitter electrode and a point of reference potential and biased for forward conduction; and a source of variable gain control voltage coupled to said transistor for simultaneously controlling the forward bias of said transistor and said PIN diode.
Claim 9
Dependent Claim
85 words
A gain controlled amplifier comprising: a transistor including base, emitter and collector electrodes and a forward biased base-to-emitter junction; a source of input signals coupled to said base electrode; a load impedance coupled to said collector electrode; a PIN diode direct current coupled between said emitter electrode and a point of signal reference potential and biased for forward conduction; and a source of variable gain control voltage coupled to said PIN diode for simultaneously controlling the forward bias of said transistor and said PIN diode.
Claim 10
Dependent Claim
85 words
A gain controlled amplifier comprising: a transistor including base, emitter and collector electrodes and a forward biased base-to-emitter junction; a source of input signals coupled to said base electrode; a load impedance coupled to said collector electrode; a PIN diode direct current coupled between said emitter electrode and a point of signal reference potential and biased for forward conduction; and a source of variable gain control voltage coupled to said PIN diode for simultaneously controlling the forward bias of said transistor and said PIN diode.
Claim 11
Dependent Claim
83 words
A gain controlled amplifier comprising: an NPN transistor including base, emitter and collector electrodes; a source of input signals coupled to said base electrode; a load impedance coupled to said collector electrode; a PIN diode having an anode direct current coupled to said emitter electrode and a cathode coupled to a source of reference potential; and a source of variable gain control voltage coupled to the base of said transistor for simultaneously varying the forward biasing of said transistor and said PIN diode.
Claim 12
Dependent Claim
83 words
A gain controlled amplifier comprising: an NPN transistor including base, emitter and collector electrodes; a source of input signals coupled to said base electrode; a load impedance coupled to said collector electrode; a PIN diode having an anode direct current coupled to said emitter electrode and a cathode coupled to a source of reference potential; and a source of variable gain control voltage coupled to the base of said transistor for simultaneously varying the forward biasing of said transistor and said PIN diode.
Claim 13
Dependent Claim
104 words
A gain controlled amplifier comprising: a transistor including base, emitter, and collector electrodes; a source of input signals coupled to said base electrode; a load impedance coupled to said collector electrode; a PIN diode direct current coupled between said emitter electrode and source of reference potential, and operated in a forward biased condition; a resistor direct current coupled in parallel with said PIN diode, the D.C. voltage across said resistor being equal to the D.C. voltage across said PIN diode; and a source of gain control voltage coupled to said transistor for simultaneously varying the forward biasing of said transistor and said PIN diode.
Claim 14
Dependent Claim
104 words
A gain controlled amplifier comprising: a transistor including base, emitter, and collector electrodes; a source of input signals coupled to said base electrode; a load impedance coupled to said collector electrode; a PIN diode direct current coupled between said emitter electrode and source of reference potential, and operated in a forward biased condition; a resistor direct current coupled in parallel with said PIN diode, the D.C. voltage across said resistor being equal to the D.C. voltage across said PIN diode; and a source of gain control voltage coupled to said transistor for simultaneously varying the forward biasing of said transistor and said PIN diode.
Claim 15
Dependent Claim
62 words
The gain controlled amplifier of claim 7, wherein said gain control voltage is variable over a range of voltages including a first range in which the transconductance of said transistor and the impedance of said PIN diode are varied and a second range in which the transconductance of said transistor is substantially constant and the impedance of said PIN diode is varied.
Claim 16
Dependent Claim
25 words
The intermediate frequency amplifier of claim 7, wherein said transistor, said PIN diode and said resistor are located on a single monolithic integrated circuit chip.
Claim 17
Dependent Claim
163 words
A gain controlled amplifier comprising: a transistor having base, emitter, and collector electrodes; a source of input signals coupled to said base electrode; a load impedance coupled to said collector electrode; and a PIN diode comprising a first localized region of high resistivity semiconductor material having a substantially planar surface; second and third localized regions of one type conductivity located in said high resistivity region adjacent to said surface; and a fourth localized region of opposite type conductivity located in said high resistivity region adjacent to said surface and intermediate said second and third localized regions, said fourth localized region being separated from said second and third regions by zones of said high resistivity semiconductor material and direct current coupled to said emitter electrode; means for electrically connecting said second and third localized regions to a source of reference potential; and a source of gain control voltage coupled to said transistor for simultaneously varying the bias of said transistor and said PIN diode.
Claim 18
Dependent Claim
163 words
A gain controlled amplifier comprising: a transistor having base, emitter, and collector electrodes; a source of input signals coupled to said base electrode; a load impedance coupled to said collector electrode; and a PIN diode comprising a first localized region of high resistivity semiconductor material having a substantially planar surface; second and third localized regions of one type conductivity located in said high resistivity region adjacent to said surface; and a fourth localized region of opposite type conductivity located in said high resistivity region adjacent to said surface and intermediate said second and third localized regions, said fourth localized region being separated from said second and third regions by zones of said high resistivity semiconductor material and direct current coupled to said emitter electrode; means for electrically connecting said second and third localized regions to a source of reference potential; and a source of gain control voltage coupled to said transistor for simultaneously varying the bias of said transistor and said PIN diode.
Claim 19
Dependent Claim
45 words
The gain controlled amplifier of claim 10, further comprising: a second transistor for coupling said load impedance to the collector electrode of said first transistor, said second transistor being arranged in a common base configuration, wherein said first and second transistors comprise a cascode amplifier.
Claim 20
Dependent Claim
30 words
The gain controlled amplifier of claims 10 or 11, further comprising a resistor direct current coupled between said emitter electrode of said first transistor and said source of reference potential.
Claim 21
Dependent Claim
69 words
The gain controlled amplifier of claim 12, further comprising a third transistor having a collector electrode coupled to a source of supply voltage, a base electrode and an emitter electrode, wherein said input signal source and said gain control voltage source are coupled to the base electrode of said third transistor, and the emitter electrode of said third transistor is coupled to the base electrode of said first transistor.
Claim 22
Dependent Claim
27 words
The gain controlled amplifier of claim 13, further comprising: a second resistor coupled between the emitter electrode of said third transistor and said source of reference potential.
Claim 23
Dependent Claim
32 words
The gain controlled amplifier of claim 14, wherein said first, second and third transistors, said first and second resistors and said PIN diode are constructed on a single monolithic integrated circuit chip.
References Cited (Backward Citations)
US3309617A
Cited
US3374404A
Cited
US3396317A
Cited
US3518585A
Cited
US3536934A
Cited
US3538448A
Cited
US3624561A
Cited
US3813602A
Cited
US3800229A
Cited
US3942181A
Cited
US4143383A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-06-22 | 1984-12-22 | 1985-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-06-22 | 1988-12-22 | 1989-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-06-22 | 1992-12-22 | 1993-06-23 | $7700.00 | Window Closed / Lapsed |