Two switchable resistive element per cell memory array

Claim 2

A memory array having a plurality of word lines and a plurality of bit lines interconnected at their intersection by a plurality of memory cells, each of said memory cells comprising a first switch means interconnecting a word line and a bit line, and a first resistive means in series between said first switch means and said bit line switchable from a high resistance state to a low resistance state when a potential above its threshold is applied, a reference cell per word line comprising a second switch means interconnecting a word line and all bit lines, and a second resistive means in series between said second switch means and all bit lines switchable from a high resistance state to a low resistance state when a potential above its threshold is applied, and output means interconnecting said reference cells and all bit lines for providing, when a memory cell is addressed by a ramp potential, a first logic output when the threshold difference of said first and second resistive means is relatively large and a second logic output when the threshold difference of said first and second resistive means is relatively small.

Claim 3

The memory array according to claim 1 wherein said output means includes a plurality of third switch means one connected to each bit line and activated by bit addressing to provide an array output and means connected between said second resistive means and said plurality of third switch means for deactivating said third switch means after said second resistive means switches to a low resistance state.

Claim 4

The memory array according to claim 2 wherein said deactivating means includes means for delaying the deactivation of said third switch means after a second resistive means switches to a low state.

Claim 5

In a memory array having a plurality of word lines and a plurality of bit lines interconnected at their intersections by a plurality of memory cells, each of said memory cells includes resistive means switchable from a high resistance state to a low resistance state when a potential above its threshold is applied, the array further comprising: a reference cell per word line having a reference resistive means switchable from a high resistance state to a low resistance state when a potential above its threshold is applied; and output means interconnecting said reference cells and all bit lines for preventing, when the array is addressed with a ramp potential, an array output if the addressed cell has a relatively high threshold voltage and for permitting an array output if the addressed cell has a relatively low threshold voltage.

Claim 6

In a memory array having a plurality of word lines and a plurality of bit lines interconnected at their intersections by a plurality of memory cells, each of said memory cells includes resistive means switchable from a high resistance state to a low resistance state when a potential above its threshold is applied, the array further comprising: a reference cell per word line having a reference resistive means switchable from a high resistance state to a low resistance state when a potential above its threshold is applied; and output means interconnecting said reference cells and all bit lines for preventing, when the array is addressed with a ramp potential, an array output if the addressed cell has a relatively high threshold voltage and for permitting an array output if the addressed cell has a relatively low threshold voltage.

Claim 7

The memory array according to claim 4 wherein said reference resistive means has a relatively high threshold voltage, and said output means include switch means for permitting an array output before said reference resistive means switches to said low resistance state and preventing an array output after said reference resistive means switches to said low resistance state.

Claim 8

The memory array according to claim 4 wherein said reference resistive means has a relatively low threshold voltage, and said output means includes bit switch means interconnecting said bit lines and the array output, and means interconnecting said bit switch means and said reference cells for deactivating said bit switch means a fixed period after said reference resistive means switches to a low resistance state, said fixed period being of shorter duration than the time difference of switching between a low threshold resistive means and a high threshold resistive means.

Claim 9

The memory array according to claim 4 wherein the threshold of said resistive means is programmable.

Claim 10

In a memory array having a plurality of word lines and a plurality of bit lines interconnected at their intersections by a plurality of memory cells, each of sid memory cells includes resistive means switchable from a high resistance state to a low resistance state when a potential above its threshold is applied, bit switch means per bit line for interconnecting a respective bit line and the array output when the bit line is addressed, the array further comprising: a reference cell per word line having a reference resistive means switchable from a high resistance state to a low resistance state when a potential above its threshold is applied; and output disable means interconnecting said reference cells and said bit switch means for deactivating said bit switch after said reference resistive means switches from a high resistance state to a low resistance state.

Claim 11

In a memory array having a plurality of word lines and a plurality of bit lines interconnected at their intersections by a plurality of memory cells, each of sid memory cells includes resistive means switchable from a high resistance state to a low resistance state when a potential above its threshold is applied, bit switch means per bit line for interconnecting a respective bit line and the array output when the bit line is addressed, the array further comprising: a reference cell per word line having a reference resistive means switchable from a high resistance state to a low resistance state when a potential above its threshold is applied; and output disable means interconnecting said reference cells and said bit switch means for deactivating said bit switch after said reference resistive means switches from a high resistance state to a low resistance state.

Claim 12

The memory array according to claim 8 wherein said output disable means include an output switch means connected to said bit switch means for deactivating said bit switch means when said output switch means is activated and a time delay means interconnecting said reference cells and said output switch means for activating said output switch a fixed period after said reference resistive means switches to a low resistance state, said fixed period being of a shorter duration than the period between the switching of a low threshold and high threshold resistive means when addressed with a ramp potential.

Claim 13

The memory array according to claim 8 wherein the threshold of said resistive means in each cell is prorammable by a write operation and said output disable means includes enable switch means for enabling said output disable means during read and disabling said output disable means during a write.

Claim 14

In a memory array having a plurality of word lines and a plurality of bit lines interconnected at their intersections by a plurality of memory cells, said memory cells comprising: first switch means interconnecting a word line and a bit line; a first bistable resistor, switchable from a high resistance state to a low resistance state for a potential applied above its threshold value, in series with said first switch means and said bit line; a second switch means interconnecting said word line and said bit line; a second bistable resistor, switchable from a high resistance state to a low resistance state for a potential applied above its threshold value, in series with said second switch means and said bit line; and output means connected between said first and second bistable resistors and said bit line for providing a first logic output on said bit line when the cell is addressed by a ramp potential and when the threshold difference of said first and second bistable resistor is relatively large and for providing a second logic output on said bit line when the threshold difference of the first and second bistable resistors is relatively small.

Claim 15

In a memory array having a plurality of word lines and a plurality of bit lines interconnected at their intersections by a plurality of memory cells, said memory cells comprising: first switch means interconnecting a word line and a bit line; a first bistable resistor, switchable from a high resistance state to a low resistance state for a potential applied above its threshold value, in series with said first switch means and said bit line; a second switch means interconnecting said word line and said bit line; a second bistable resistor, switchable from a high resistance state to a low resistance state for a potential applied above its threshold value, in series with said second switch means and said bit line; and output means connected between said first and second bistable resistors and said bit line for providing a first logic output on said bit line when the cell is addressed by a ramp potential and when the threshold difference of said first and second bistable resistor is relatively large and for providing a second logic output on said bit line when the threshold difference of the first and second bistable resistors is relatively small.

Claim 16

The memory array according to claim 11 wherein said output means includes a third switch means connected to said bit line and activated by bit addressing to provide an array output and time delay means interconnecting said second bistable resistor and said third switch means for deactivating said third switch means a fixed time after said second bistable resistor switches to a low resistance state.

Claim 17

The memory array according to claim 12 wherein said first and second switch means are bipolar transistors connected as emitter follower and said third switch means is an insulated gate field effect transistor.

Claim 18

The memory array according to claim 13 wherein said time delay means includes a fourth switch means connected to the gate of said insulated gate field effect transistor for grounding said gate after said fixed time to deactivate said insulated gate field effect transistor.

Claim 19

The memory array according to claim 12 wherein said first and second bistable resistors are amorphous semiconductor elements.

Claim 22

The method according to claim 16 wherein said reference resistive means are provided with high threshold values.

Claim 23

The method according to claim 16 wherein said reference resistive means are provided with low threshold values and including the step or delaying the operation of said output disabling means for a time period shorter than said first time period.