Nonvolatile semiconductor memory apparatus

Claim 2

A nonvolatile semiconductor memory apparatus comprising: a flip-flop circuit formed of a pair of gate insulated field effect transistors and having bistable output terminals; a memory section having at least one memory cell, said memory cell having a pair of nonvolatile memory cell elements whose memory state can be repeatedly changed and which are coupled to said bistable output terminals of said flip-flop circuit, respectively; shortcircuiting means for selectively shortcircuiting the current paths of said pair of gate insulated field effect transistors; and control voltage supply means for applying a control voltage to said memory cell elements for setting a mode of operation of said memory cell.

Claim 3

The nonvolatile semiconductor memory apparatus according to claim 1 wherein said pair of nonvolatile memory cell elements are formed of a pair of variable threshold voltage field effect transistors having the current paths coupled to said bistable output terminals of said flip-flop circuit, respectively, and the gate coupled to said control voltage supply means.

Claim 4

The nonvolatile semiconductor memory apparatus according to claim 1 or 2, further comprising voltage signal supply means for applying a predetermined voltage signal to said bistable output terminals of said flip-flop circuit.

Claim 5

The nonvolatile semiconductor memory apparatus according to claim 1 or 2, wherein said memory section has a plurality of memory cells arrayed in matrix.

Claim 6

The nonvolatile semiconductor memory apparatus according to claim 4, which further comprises plural pairs of switching elements arranged for respective columns and means for selectively energizing said pairs of switching elements, and in which said pairs of memory cell elements forming those of said memory cells which are arranged in the same column are coupled through said pair of switching elements to said bistable output terminals of said flip-flop circuit, respectively.

Claim 7

The nonvolatile semiconductor memory apparatus according to claim 1 or 2, wherein said shortcircuiting means includes a pair of gate insulated field effect transistors coupled to have the current paths in parallel with the current paths of said pair of gate insulated field effect transistors, respectively.

Claim 8

The nonvolatile semiconductor memory apparatus according to claim 1, wherein said pair of nonvolatile memory cell elements are formed of a pair of nonvolatile MNOS capacitors having sources coupled to said bistable output terminals of said flip-flop circuit, respectively and the gates coupled to said control voltage supply means.

Claim 9

The nonvolatile semiconductor memory apparatus according to claim 7, further comprising voltage signal supply means for applying a predetermined voltage signal to said bistable output terminals of said flip-flop circuit.

Claim 10

The nonvolatile semiconductor memory apparatus according to claim 7, wherein said memory section has a plurality of memory cells arrayed in matrix.

Claim 11

The nonvolatile semiconductor memory apparatus according to claim 9, which further comprises pairs of switching elements arranged for respective columns and means for selectively energizing said pairs of switching elements, and in which said pair of memory cell elements froming those of said memory cells which are arranged in the same column are coupled through said pair of switching elements to said bistable output terminals of said flip-flop circuit, respectively.

Claim 12

The nonvolatile semiconductor memory apparatus according to claim 7, wherein said shortcircuiting means includes pair of gate insulated field effect transistors coupled to have the current paths in parallel with the current paths of said pair of gate insulated field effect transistors, respectively.

Claim 13

A nonvolatile semiconductor memory apparatus comprising: a plurality of flip-flop circuits each formed of a pair of gate insulated field effect transistors and having bistable terminals; a memory section coupled to each of said flip-flop circuits, and having at least one memory cell, said memory cell including a pair of nonvolatile memory cell elements whose memory state can be repeatedly changed and which are coupled to said bistable output terminals of the respective flip-flop circuits; shortcircuiting means for selectively shortcircuiting the current paths of said pair of gate insulated field effect transistors; control voltage supply means for applying a control voltage to said memory cell elements for setting a mode of operation of said memory cell; a plurality of cascade-connected shift register circuits; and data transfer control means coupled between said plurality of flip-flop circuits and cascade-connected shift register circuits for controlling a data transfer between said flip-flop circuits and shift register circuits.

Claim 14

A nonvolatile semiconductor memory apparatus comprising: a plurality of flip-flop circuits each formed of a pair of gate insulated field effect transistors and having bistable terminals; a memory section coupled to each of said flip-flop circuits, and having at least one memory cell, said memory cell including a pair of nonvolatile memory cell elements whose memory state can be repeatedly changed and which are coupled to said bistable output terminals of the respective flip-flop circuits; shortcircuiting means for selectively shortcircuiting the current paths of said pair of gate insulated field effect transistors; control voltage supply means for applying a control voltage to said memory cell elements for setting a mode of operation of said memory cell; a plurality of cascade-connected shift register circuits; and data transfer control means coupled between said plurality of flip-flop circuits and cascade-connected shift register circuits for controlling a data transfer between said flip-flop circuits and shift register circuits.

Claim 15

The nonvolatile semiconductor memory apparatus according to claim 12, wherein said pair of nonvolatile memory cell elements are formed of a pair of variable threshold field effect transistors having the current paths coupled to said bistable output terminals of said flip-flop circuit, respectively, and the gates coupled to said control voltage supply means.

Claim 16

The nonvolatile semiconductor memory apparatus according to claim 12 or 13, further comprising voltage signal supply means for applying prescribed voltage signal to said bistable output terminals of said flip-flop circuits.

Claim 17

The nonvolatile semiconductor memory apparatus according to claim 12 or 13, wherein said shortcircuiting means includes a pair of gate insulated field effect transistors coupled to have the current paths in parallel with the current paths of said pair of gate insulated field effect transistors, respectively.

Claim 18

The nonvolatile semiconductor memory apparatus according to claim 12, wherein said pair of nonvolatile memory cell elements are formed of a pair of nonvolatile MNOS capacitors having sources coupled to said bistable output terminals of said flip-flop circuit, respectively and the gates coupled to said control voltage supply means.

Claim 19

The nonvolatile semiconductor memory apparatus according to claim 16, further comprising voltage signal supply means for applying a predetermined voltage signal to said bistable output terminals of said flip-flop circuit.

Claim 20

The nonvolatile semiconductor memory apparatus according to claim 16, wherein said shortcircuiting means includes pair of gate insulated field effect transistors coupled to have the current paths in parallel with the current paths of said pair of gate insulated field effect transistors, respectively.