Delay line time compression correlation circuit

Claim 2

A delay line time compression correlation circuit utilizing a clock signal, comprising: control counting means responsive to the clock signal for providing a first output indicative of correlation count and a second output indicative of beam position; first and second storage means for sampling and storing respective input data for correlation; first and second recirculating means for respectively receiving data from said first and second storage means, said first and second recirculating means providing respective sample outputs; sample controlling means responsive to said control counting means for controlling the sampling and storing functions of said first and second storage means, and for controlling the transfer of data from said first and second storage means to said first and second recirculating means; correlating means responsive to said respective sample outputs for providing a series of correlation outputs; and correlation counting means responsive to said control counting means and said correlation output for accumulating said correlation outputs and for providing an individual accumulation output associated with each beam position, said accumulation output being provided during the correlation of a beam position other than the beam position associated with said accumulation output.

Claim 3

The correlation circuit of claim 1 wherein said control counting means comprises a binary counter providing predetermined low order output bits as said first output indicative of correlation count and predetermined output bits of higher order than said low order output bits as said second output indicative of beam position.

Claim 4

The correlation circuit of claim 1 wherein said first and second recircuating means respectively comprise first and second shift registers selectively controlled to recirculate by said sample controlling means, said first shift register having one more stage than said second shift register.

Claim 5

The correlation circuit of claim 3 wherein the number of stages in said first shift register is determined by the number of distinct states provided by said first output of said control counting means.

Claim 6

The correlation circuit of claim 1 wherein said sample controlling means allows respective new input samples to be read into said first and second storage means as a function of the change of the value of said control counting means second output indicative of beam position.

Claim 7

The correlation circuit of claim 1 wherein said correlating means comprises an exclusive NOR gate.

Claim 8

The correlation circuit of claim 1 wherein said correlation counting means includes first and second counters selectively enabled to accept said correlation outputs as inputs as a function of said control counting means first output.

Claim 9

A delay line time compression correlation circuit utilizing a clock signal, comprising: control counting means responsive to the clock signal for providing a first output indicative of correlation count and a second output indicative of beam position; first and second storage means for sampling and storing respective input data for correlation; first and second recirculating means for respectively receiving data from said first and second storage means, each said first and second recirculating means synchronously providing a respective sample output on each occurrence of a predetermined transition of the clock signal, thereby providing a pair of sample outputs on each such occurrence of said predetermined clock signal transition; sample controlling means responsive to said control counting means for controlling the sampling and storing functions of said first and second storage means, and for controlling the transfer of data from said first and second storage means to said first and second recirculating means, said sampling and storing functions sychronously occurring for said first and second storage means in response to a predetermined value of said control counting means first output; and correlation means responsive to each pair of sample outputs from said first and second recirculating means for providing a correlation result for each sample output pair, and for providing a total correlation result for a predetermined number of first and second recirculating means output pairs.

Claim 10

A delay line time compression correlation circuit utilizing a clock signal, comprising: control counting means responsive to the clock signal for providing a first output indicative of correlation count and a second output indicative of beam position; first and second storage means for sampling and storing respective input data for correlation; first and second recirculating means for respectively receiving data from said first and second storage means, each said first and second recirculating means synchronously providing a respective sample output on each occurrence of a predetermined transition of the clock signal, thereby providing a pair of sample outputs on each such occurrence of said predetermined clock signal transition; sample controlling means responsive to said control counting means for controlling the sampling and storing functions of said first and second storage means, and for controlling the transfer of data from said first and second storage means to said first and second recirculating means, said sampling and storing functions sychronously occurring for said first and second storage means in response to a predetermined value of said control counting means first output; and correlation means responsive to each pair of sample outputs from said first and second recirculating means for providing a correlation result for each sample output pair, and for providing a total correlation result for a predetermined number of first and second recirculating means output pairs.

Claim 11

The correlation circuit of claim 8 wherein said sample and store functions occur on said predetermined clock signal transition under the control of said sample controlling means.

Claim 12

The correlation circuit of claim 8 wherein said first and second recirculating means respectively comprise first and second clocked shift registers selectively controlled to shift or recirculate by said sample controlling means, said first and second clock shift registers being responsive to said predetermined clock signal transition.

Claim 13

The correlation circuit of claim 8 wherein said sample controlling allows respective new input samples to be read into said first and second storage means as a function of the change of the value of said control counting means second output indicative beam position.

Claim 14

The correlation circuit of claim 8 wherein said sample controlling means comprises: first logic means responsive to said control counting means first output for enabling first and second storage means to sample and store data in response to said predetermined value of said first output indicative of correlation count and for enabling said second recirculating means to accept data from said second storage means in response to said predetermined value of said control counting means first output; and second logic means responsive to said control counting means second output for enabling said first recirculating means to accept data from said first storage means in response to a predetermined value of said second output.

Claim 15

The correlation circuit of claim 8 wherein said correlation means includes first and second counters which are alternately enabled as a function of the change of said control counting means second output to count said correlation results.