Color television receiver comprising at least one integrated circuit for the luminance signal and the chrominance signals

Claim 1

A color-television receiver, comprising: at least one integrated circuit for separating and conditioning the luminance signal and the chrominance signals from the composite color signal, said integrated circuit including a chrominance-subcarrier oscillator, a chrominance-subcarrier band-pass filter, a synchronous demodulator, a PAL switch, a color matrix and an R-G-B matrix, said chrominance-subcarrier oscillator is a square-wave clock generator providing four clock signals, the first of which has four times the chrominance-subcarrier frequency, and the second to fourth of which have the chrominance-subcarrier frequency, with the first and second clock signals having a mark-to-space ratio of 0.5, and the third and fourth clock signals each consisting of two consecutive, T/2-long pulses separated by T/2 within each 4T-long period (T=period of the first clock signal); an analog-to-digital converter clocked by the first clock signal, whose analog input is presented with the composite color signal, and which forms as its output signal a parallel binary word from the amplitude of the composite color signal at those instants where the respective amplitudes of the undemodulated chrominance signal are equal to the amplitudes of the respective color-difference signal; a first binary arithmetic stage which multiplies the output signal of the analog-to-digital converter by a binary overall-contrast control signal; a two-stage delay line which delays the output signal of the first binary arithmetic stage by T/2; a second binary arithmetic stage which forms the arithmetic means of the delayed and undelayed output signals of the first binary arithmetic stage; a third binary arithmetic stage which subtracts the output signal of the second binary arithmetic stage from the output signal of the first delay stage; a buffer-memory arrangement which temporarily stores the output signal of the third binary arithmetic stage and whose enable input is fed with the third clock signal; a shift-register arrangement consisting of n parallel shift registers (n=number of bits at the output of the third binary arithmetic stage) each of which provides a delay of one line period and whose serial inputs are connected to the parallel outputs of the buffer-memory arrangement while their clock inputs are fed with the fourth clock signal; a fourth binary arithmetic stage which forms the arithmetic mean of the input and output signals of the shift-register arrangement; a fifth binary arithmetic stage which subtracts the input signal of the shift-register arrangement from the output signal of this arrangement and then divides the difference obtained by two; a sixth binary arithmetic stage which, controlled by the PAL switch, either leaves the output signal of the fifth binary arithmetic stage unchanged or forms its absolute value; and a seventh binary arithmetic stage which forms the green color-difference signal from the output signals of the fourth and sixth binary arithmetic stages, the outputs of the second, fourth, sixth and seventh binary arithmetic stages are connected to the binary R-G-B matrix, each of whose outputs is coupled to one of three digital-to-analog converters for deriving the analog signals for controlling the R-G-B values of the picture tube.