§
Luxuse
Patent Intelligence
Sign In
← Back to Patent Explorer
US4263561A Expired / Lapsed US ⏱️ 0.0 years remaining

Amplifier arrangement with suppression of spurious signals

Assignee: GE Medical Systems Information Technologies GmbH
•
Filing: 1979-07-05
•
Granted: 1981-04-21
•
Expires: 1999-07-05
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract For the common mode rejection in an amplifier arrangement comprising preferably a plurality of operational amplifiers for a plurality of desired signals to be processed, which signals are superimposed by a stronger spurious signal, it is an object to supply the desired signals such as physiological measuring signals for EEG and EKG measurements at positive inputs of the respectively associated single amplifiers, while each negative input is connected to the junction of a voltage divider consisting of two resistors, which voltage divider is arranged between the respective amplifier output and a reference potential. This reference potential is determined by the output of an additional operational amplifier, to the positive input of which a desired signal superimposed by the same spurious signal is applied, while the negative input thereof is connected to the junction of a voltage divider consisting of two resistors, which voltage divider is connected between the output of the additional operational amplifier and the reference potential. Accordingly, in signal amplifiers for measuring purposes such as for physiological measuring signals the common mode rejection is already achieved in the preamplifier stages to that separate differential stages for the common mode rejection may be saved.

Inventors

  • 👤 Horst Weber

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 06:35
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45475; H03F3/45479; H03F3/45928; H03F3/45968; H03F3/45991

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 225 words
An improved amplifier arrangement for a plurality of individually generated desired signals to be processed, upon which useful signals a relatively stronger noise signal is superimposed, comprising a plurality of like single amplifiers, each having a positive and a negative input terminal, wherein each positive input terminal receives a specific useful signal having the spurious signal superimposed thereon, and wherein each negative input terminal is connected to the output terminal of the respective amplifier via an associated first resistor and to a bus line common to all single amplifiers at a common potential via an associated second resistor, the ratio of resistance values between interconnected first and second resistors being the same for all single amplifiers, wherein the improvement comprises: an additional amplifier having a positive and a negative input terminal, which additional amplifier has its output terminal connected to the bus line, the output terminal of the additional amplifier being connected to the negative input terminal via a third resistor, the negative input terminal in turn being connected to a reference potential through a fourth resistor, while one of the useful signals is applied to the positive input terminal of the additional amplifier, the ratio between the resistance values of the third and fourth resistors being equal to the reciprocal of the ratio of the resistance values between the interconnected first and second resistors.
Claim 2
Dependent Claim 225 words
An improved amplifier arrangement for a plurality of individually generated desired signals to be processed, upon which useful signals a relatively stronger noise signal is superimposed, comprising a plurality of like single amplifiers, each having a positive and a negative input terminal, wherein each positive input terminal receives a specific useful signal having the spurious signal superimposed thereon, and wherein each negative input terminal is connected to the output terminal of the respective amplifier via an associated first resistor and to a bus line common to all single amplifiers at a common potential via an associated second resistor, the ratio of resistance values between interconnected first and second resistors being the same for all single amplifiers, wherein the improvement comprises: an additional amplifier having a positive and a negative input terminal, which additional amplifier has its output terminal connected to the bus line, the output terminal of the additional amplifier being connected to the negative input terminal via a third resistor, the negative input terminal in turn being connected to a reference potential through a fourth resistor, while one of the useful signals is applied to the positive input terminal of the additional amplifier, the ratio between the resistance values of the third and fourth resistors being equal to the reciprocal of the ratio of the resistance values between the interconnected first and second resistors.
Claim 3
Dependent Claim 32 words
Amplifier arrangement according to claim 1, wherein the first resistors are selected to have all the same resistance value and the second resistors are also selected to have the same resistance value.
Claim 4
Dependent Claim 43 words
Amplifier arrangement according to claim 2, wherein the resistance value of the third resistor is equal to that of one of the second resistors and that the resistance value of the fourth resistor is equal to that of one of the first resistors.
Claim 5
Dependent Claim 25 words
Amplifier arrangement in accordance with claim 2 or claim 3, wherein each of the single amplifiers is an operational amplifier with the same characteristic values.
Claim 6
Dependent Claim 22 words
Amplifier arrangement according to claim 4, wherein the additional amplifier is an amplifier having a high amplification factor, preferably an operational amplifier.
Claim 7
Dependent Claim 40 words
Amplifier arrangement in accordance with claim 5, wherein the outputs of the single amplifiers can be switched selectively and by pairs over a selector circuit to the negative and positive input respectively of one of a plurality of differential amplifiers.

References Cited (Backward Citations)

US3725804A Cited
US3906384A Cited
US4152659A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1984-04-20 1984-10-20 1985-04-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1988-04-20 1988-10-20 1989-04-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1992-04-20 1992-10-20 1993-04-21 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag