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US3906384A
Expired / Lapsed
US
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System for nullifying signal processor distortions
Assignee: VSC Co WESTPORT CT A OF LP
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Filing: 1973-02-12
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Granted: 1975-09-16
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Expires: 1993-02-12
Abstract
Abstract A system for nullifying characteristic disturbances introduced into an analog information signal passing through a multiple stage signal processor which is varied in one or more parameters, such as an analog shift register whose shift rate is repetetively varied and recycled between two rates. In one embodiment, an inverter is placed midway through the register so that the characteristic distortions effected in the signal during transmission through the first half of the stages are selfcanceled through the remaining half while the signal, though inverted, is transmitted. In another embodiment of the invention, the signal and its inverse are fed respectively through two full length (N-stage) registers, the outputs of which are connected respectively to the inverting and non-inverting inputs of a summing circuit. Since the signal applied to one of these inputs as well as one of the register output signals are inverted, the summed information signal is provided at twice the unsummed amplitude and with a nullification of the characteristic distortions effected by processing through the register. In a modification of the second embodiment, the signal and its inverse are alternately sampled and fed respectively through each of two half-length registers (N/2 stages) (which are thus equivalent respectively to the odd and even stages of a single register), one of the outputs of which is inverted before being applied alternately with the non-inverted other output to the summing amplifier, thus yielding a full composite signal of normal amplitude and also a sequential sample-by-sample nullification of said characteristic distortions.
Inventors
- 👤 Murray M Schiffman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:10
CPC Classifications
H; H04; H04B; H04B15/00
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
93 words
A signal processing circuit comprising: first and second multi-stage processing components through which said signal is serially transmitted, said first and second components each distorting said signal cumulatively through a plurality of stages in substantially the same characteristic manner; and, means interposed between said first and second components for inverting the output of said first processing component and applying the inverted output as the sole input to said second processing component to cancel the distortion introduced in said signal by said first processing component with the distortion introduced by said second processing component.
Claim 2
Dependent Claim
93 words
A signal processing circuit comprising: first and second multi-stage processing components through which said signal is serially transmitted, said first and second components each distorting said signal cumulatively through a plurality of stages in substantially the same characteristic manner; and, means interposed between said first and second components for inverting the output of said first processing component and applying the inverted output as the sole input to said second processing component to cancel the distortion introduced in said signal by said first processing component with the distortion introduced by said second processing component.
Claim 3
Dependent Claim
96 words
A signal processing circuit comprising: first and second processing components through which said signal and its inverse are respectively transmitted in parallel, said first and second components presenting corresponding portions of said signal and its inverse at their respective outputs, said corresponding portions having substantially identical distortion characteristics effected by transmission through said processing components; a summing circuit having an inverting and noninverting input for respectively receiving the outputs of said first and second processing components to substantially cancel the inverted and non-inverted distortion characteristics outputted from said summing circuit while additively combining said corresponding portions.
Claim 4
Dependent Claim
96 words
A signal processing circuit comprising: first and second processing components through which said signal and its inverse are respectively transmitted in parallel, said first and second components presenting corresponding portions of said signal and its inverse at their respective outputs, said corresponding portions having substantially identical distortion characteristics effected by transmission through said processing components; a summing circuit having an inverting and noninverting input for respectively receiving the outputs of said first and second processing components to substantially cancel the inverted and non-inverted distortion characteristics outputted from said summing circuit while additively combining said corresponding portions.
Claim 5
Dependent Claim
107 words
An analog signal processor comprising analog shift register means for transferring analog signals through a pair of analog shift registers each of said registers having a like plurality of serial analog shift stages, said stages introducing transfer signal components which degrade said analog signals; means for supplying an analog signal and its inverse as the respective inputs of said registers; and means effectively differentially combining the outputs of said registers for producing an output processed analog signaL having said transfer signal components substantially cancelled by the inverse combination of said components introduced by said pair of registers while additively combining said analog signals transferred through said registers.
Claim 6
Dependent Claim
107 words
An analog signal processor comprising analog shift register means for transferring analog signals through a pair of analog shift registers each of said registers having a like plurality of serial analog shift stages, said stages introducing transfer signal components which degrade said analog signals; means for supplying an analog signal and its inverse as the respective inputs of said registers; and means effectively differentially combining the outputs of said registers for producing an output processed analog signaL having said transfer signal components substantially cancelled by the inverse combination of said components introduced by said pair of registers while additively combining said analog signals transferred through said registers.
Claim 7
Dependent Claim
103 words
An analog signal processor comprising: analog shift register means for transferring sampled analog signals through a pair of analog shift registers, each of said registers having a like plurality of serial analog shift stages, said stages introducing transfer signal components which degrade said analog signals; means for supplying an analog input signal direct to one register and inverted to the other register of said pair of registers; and means for inversely combining the outputs of said pair of registers to produce an output processed analog signal having said transfer signal components substantially cancelled while additively combining said analog signals transferred through said registers.
Claim 8
Dependent Claim
103 words
An analog signal processor comprising: analog shift register means for transferring sampled analog signals through a pair of analog shift registers, each of said registers having a like plurality of serial analog shift stages, said stages introducing transfer signal components which degrade said analog signals; means for supplying an analog input signal direct to one register and inverted to the other register of said pair of registers; and means for inversely combining the outputs of said pair of registers to produce an output processed analog signal having said transfer signal components substantially cancelled while additively combining said analog signals transferred through said registers.
Claim 9
Dependent Claim
51 words
A processor according to claim 4 in which said analog shift registers process said direct and inverted analog signal in parallel and said means for inversely combining the outputs of said pair of registers inverts the output of said one register for combination with the direct output of said other register.
Claim 10
Dependent Claim
34 words
A processor according to claim 5 in which said means for inversely combining includes means for additively combining the magnitudes of said outputs to approximately double the magnitude of said output processed analog signal.
Claim 11
Dependent Claim
123 words
An analog signal processor comprising: a pair of analog shift registers each having a like plurality of serial analog shift stages; means for supplying an analog signal input direct to one register and inverted to the other register of said pair of registers; means for applying out of phase clocking signals to said pair of registers to alternately direct and transfer inverted sampled values of said analog signal through said registers respectively, said registers introducing transfer signal components which are present with said sampled values; and means for inversely combining the outputs of said pair of registers to combine the alternate relatively inverted sampled value outputs as a replica of said analog signal and cancel said transfer signal components present in said outputs.
Claim 12
Dependent Claim
123 words
An analog signal processor comprising: a pair of analog shift registers each having a like plurality of serial analog shift stages; means for supplying an analog signal input direct to one register and inverted to the other register of said pair of registers; means for applying out of phase clocking signals to said pair of registers to alternately direct and transfer inverted sampled values of said analog signal through said registers respectively, said registers introducing transfer signal components which are present with said sampled values; and means for inversely combining the outputs of said pair of registers to combine the alternate relatively inverted sampled value outputs as a replica of said analog signal and cancel said transfer signal components present in said outputs.
Claim 13
Dependent Claim
28 words
Apparatus according to claim 7 and including a low pass filter coupled to said last named means for passing said replica and blocking sampling rate transfer signal components.
Claim 14
Dependent Claim
84 words
A signal processing system comprising: first and second parallel storage channels for receiving and temporarily storing a signal, said first and second channels each distorting said signal in substantially the same characteristic manner; and means for inverting the signal input of one as well as the output of one of said storage channels to cancel the distortion introduced in said signal by said first storage channel with the distortion introduced by said second storage channel while additively combining the output signals from said channels.
Claim 15
Dependent Claim
84 words
A signal processing system comprising: first and second parallel storage channels for receiving and temporarily storing a signal, said first and second channels each distorting said signal in substantially the same characteristic manner; and means for inverting the signal input of one as well as the output of one of said storage channels to cancel the distortion introduced in said signal by said first storage channel with the distortion introduced by said second storage channel while additively combining the output signals from said channels.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-15 | 1979-03-17 | 1979-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-15 | 1983-03-17 | 1983-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-15 | 1987-03-17 | 1987-09-16 | $7700.00 | Window Closed / Lapsed |