Timer circuit for vending machine

Claim 2

Timer circuit for a vending machine comprising; a counter having first and second counter sections, one for demarcating coinage and another for demarcating vend period, said counter having input means for counting the counter and output lines corresponding to the sections thereof, means responsive to coinage for generating at least one count signal coupled to the input means of the counter to count the first section of the counter, circuit means for operating a load during the vend period, first settable decoder means coupled from output lines of the first section of the counter for providing a signal coupled to said circuit means for initiating the vend period of the circuit means, said counter input means including gate means receiving at least said one count signal coupling to the clock input of the counter, means for generating clock signals (coupled) for selective coupling to the gate means and in turn to the counter to count the second section of the counter, means responsive to said first settable decoder means and the vend period initiation signal therefrom for permitting the passage of the clock signals to the counter input means, and second settable decoder means coupled from output lines of the second section for providing a signal terminating the vend period of the circuit means.

Claim 3

A timer circuit as set forth in claim 1 wherein said counter is a binary counter having the least significant bit output lines coupling to the first settable decoder and the most significant bit output lines coupling to the second settable decoder.

Claim 4

A timer circuit as set forth in claim 1 wherein said settable decoders include, respectively, first and second switch means and first and second decoder gate means, said first switch means for setting the coin denomination for operation of the machine and said second switch means for setting the duration of the vend period.

Claim 5

A timer circuit as set forth in claim 3 wherein each switch means has a number of switches corresponding to the number of output lines from the counter.

Claim 6

A timer circuit as set forth in claim 1 including means intercoupling the output of the first decoder with the circuit means including a bistable device set to initiate the vend period and means responsive to the output of the second decoder for resetting the bistable device to terminate the vend period.

Claim 7

A timer circuit as set forth in claim 5 wherein said circuit means includes an AC operated electronic switch.

Claim 8

A timer circuit as set forth in claim 1 wherein said means responsive to coinage includes means responsive to coins of at least two different denominations, including first and second coin responsive circuits.

Claim 9

A timer circuit as set forth in claim 7 including means intercoupling the first and second coin responsive circuits for generating spaced pulses in both circuits in response to coinage of the larger denomination.

Claim 10

A timer circuit as set forth in claim 8 wherein said means intercoupling includes a uni-directional electronic means.

Claim 11

A timer circuit as set forth in claim 1 including means coupled from the second settable decoder means for resetting at least the counter.

Claim 12

A timer circuit as set forth in claim 10 wherein the means for resetting includes power-up reset means.

Claim 13

A timer circuit as set forth in claim 1 including means for inhibiting signals from the means responsive to coinage after the proper coinage amount has been received.

Claim 14

A timer circuit as set forth in claim 1 wherein said means for generating clock signals includes a source of pulse signals coupled to an enable gate which is only enabled after registration of the proper coinage to count the second counter section through the vend period.

Claim 15

A timer circuit as set forth in claim 13 wherein said gate means of the counter input means includes an AND type gate having one count signal path receiving the coinage count signal and at least a second path receiving the pulse signals.

Claim 16

A timer circuit as set forth in claim 14 wherein the circuit means includes a bistable device set to initiate the vend period and means responsive to the output of the second settable decoder means for resetting the bistable device to terminate the vend period and disable said enable gate to end the pulse signals.

Claim 17

A timer circuit as set forth in claim 15 including means responsive to said first settable decoder means for inhibiting further coinage count signals when the decoder means is satisfied indicating proper coinage amount.

Claim 18

A timer circuit for a vending machine comprising; a counter having first and second counter sections, said counter having input means for counting the counter and output lines corresponding to the sections thereof, means responsive to coinage for generating a signal coupled to the input means of the counter to count the counter, circuit means for operating a load during a vend period, first settable decoder means coupled from output lines of the first section of the counter for providing a signal for initiating the vend period of the circuit means, second settable decoder means coupled from output lines of the second section of the counter for providing a signal terminating the vend period of the circuit means, and means for selectably manually interrupting the vend period by inhibiting operation of the circuit means associated with the load.

Claim 19

A timer circuit for a vending machine comprising; a counter having first and second counter sections, said counter having input means for counting the counter and output lines corresponding to the sections thereof, means responsive to coinage for generating a signal coupled to the input means of the counter to count the counter, circuit means for operating a load during a vend period, first settable decoder means coupled from output lines of the first section of the counter for providing a signal for initiating the vend period of the circuit means, second settable decoder means coupled from output lines of the second section of the counter for providing a signal terminating the vend period of the circuit means, and means for selectably manually interrupting the vend period by inhibiting operation of the circuit means associated with the load.

Claim 20

Timer circuit for a vending machine comprising; a counter having first and second counter sections, one for demarcating coinage and another for demarcating vend period, said counter having input means for counting the counter and output lines corresponding to the sections thereof, means responsive to coinage for generating at least one count signal coupled to the input means of the counter to count the first section of the counter, circuit means for operating a load during the vend period, first settable decoder means coupled from output lines of the first section of the counter for providing a signal coupled to said circuit means for initiating the vend period of the circuit means, said counter input means including means defining a signal clock input line and said counter sections being contiguous with the counter being counted at the single clock input line to progress from the first to the second sections of the counter, means for generating clock signals for selective coupling to the counter clock input line to count the counter, means responsive to said first settable decoder means for permitting the clock signals to pass to said counter, and second settable decoder means coupled from output lines of the second section of the counter for providing a signal terminating the vend period of the circuit eans.

Claim 21

Timer circuit for a vending machine comprising; a counter having first and second counter sections, one for demarcating coinage and another for demarcating vend period, said counter having input means for counting the counter and output lines corresponding to the sections thereof, means responsive to coinage for generating at least one count signal coupled to the input means of the counter to count the first section of the counter, circuit means for operating a load during the vend period, first settable decoder means coupled from output lines of the first section of the counter for providing a signal coupled to said circuit means for initiating the vend period of the circuit means, said counter input means including means defining a signal clock input line and said counter sections being contiguous with the counter being counted at the single clock input line to progress from the first to the second sections of the counter, means for generating clock signals for selective coupling to the counter clock input line to count the counter, means responsive to said first settable decoder means for permitting the clock signals to pass to said counter, and second settable decoder means coupled from output lines of the second section of the counter for providing a signal terminating the vend period of the circuit eans.