Selectively adjustable voltage detection integrated circuit

Claim 2

A voltage detection circuit for use with a voltage source adapted to deliver a source voltage comprising in combination reference voltage means for producing a set reference voltage, voltage converter means for producing a converted voltage representative of the source voltage delivered by said voltage source, comparator means for receiving said set reference voltage and said converted voltage, and for providing a comparison signal in response thereto, and regulation circuit means intermediate one of said reference voltage means and converter means and comparator means for selectively varying one of said set voltage and converted voltage to be applied to said comparator means each of said regulation circuit means, reference voltage means, voltage converter means and comparator means being comprised of integrated circuit elements that are fabricated into the same circuit chip.

Claim 3

A voltage detection circuit as claimed in claim 1, and including pulse generating means for coincidentally applying differential sampling pulses of a predetermined time interval to said reference voltage means, voltage converter means, comparator means and regulation means for selectively energizing each said reference voltage means, voltage converter means, comparator means and regulation means only during said predetermined time interval that said sampling pulse is applied thereto to thereby limit the operation of said detection circuit to said predetermined intervals of time that sampling pulses are applied thereto.

Claim 4

A voltage detection circuit as claimed in claim 2, and including memory means coupled to said comparator means for storing said comparison signal produced thereby when said sampling pulses are applied to said memory means.

Claim 5

A voltage detection circuit as claimed in claim 2, wherein said pulse generating means includes a flip-flop shift register adapted to receive a first high frequency clock signal and a second lower frequency write-in signal and in reponse to the leading edge of each clock signal produce a delayed output signal having the same period as the write-in signal and delayed with respect to said write-in signal by a period equal to one-half the period of said clock signal and differential gating means adapted to receive said delayed output signal and said clock signal and in response thereto produce a differential sampling pulse signal wherein the differential sampling pulses have a duty cycle equal to one-half the period of said high frequency clock signal and occur once during each period of said lower frequency write-in signal.

Claim 6

A voltage detection circuit as claimed in claim 4, wherein the active elements defining said shift register means and said differential gating means are MOS transistors.

Claim 7

A voltage detection circuit as claimed in claim 1, wherein said voltage reference means includes at least a first pair of complementary coupled P-channel and N-channel transistors, at least one of said like polarity transistors of each complementary coupled P-channel and N-channel transistors having a different threshold voltage then the like polarity transistor in the other complementary coupled P-channel and N-channel transistors.

Claim 8

A voltage detection circuit as claimed in claim 6, wherein said reference voltage circuit includes a voltage follower operational amplifier including a current mirror defined by N-channel transistors and P-channel transistors having the same conductance coefficients as the aforementioned N-channel and P-channel transistors, respectively, and a voltage divider coupled to the output of said operational amplifier for producing said set reference voltage to be applied to said comparator in response to the reference voltage, said reference voltage being applied to said voltage follower operational amplifier means.

Claim 9

A voltage detection circuit as claimed in claim 6, wherein said reference voltage means includes a voltage divider means for linearly dividing said set reference voltage produced thereby.

Claim 10

A voltage detection circuit as claimed in claim 6, wherein said voltage reference means includes a linear resistive means for selectively dividing said reference voltage into one of at least two distinct levels, said regulation circuit means being coupled to said linear resistive means for producing said set reference voltage by selecting the distinct level of said converted voltage to be applied to said comparator means.

Claim 11

A voltage detection circuit as claimed in claim 9, wherein said linear resistive means is a voltage divider network defining a plurality of output terminals, said regulation means including a plurality of switching means, each of said switching means being coupled intermediate an output terminal of said voltage divider and said comparator means for selectively coupling each of said output terminals of said divider network to said comparator means to selectively vary said set reference voltage applied to said comparator means.

Claim 12

A voltage detection circuit as claimed in claim 9, wherein said linear resistive means is comprised of a plurality of integrated circuit resistor means.

Claim 13

A voltage detection circuit as claimed in claim 10, wherein said regulation means includes a binary control means coupled to each of said switching means for digitally selecting one of said switching means to thereby couple said respective output terminals of said resistive means coupled to said respective selected switching means associated therewith to thereby apply said set voltage to said comparator means.

Claim 14

A voltage detection circuit as claimed in claim 12, wherein said binary control means includes a plurality of non-volatile memory integrated circuit elements that are set to a predetermined binary state during fabrication thereof to thereby select a distinct level of converted voltage to be applied to the comparator means during fabrication of the regulaton circuit into the integrated circuit chip.

Claim 15

A voltage detection circuit as claimed in claim 13, wherein each of said non-volatile integrated circuit elements are FAMOS circuit elements.

Claim 16

A voltage detection circuit as claimed in claim 14, wherein each of said non-volatile integrated circuit elements are MNOS circuit elements.

Claim 17

A voltage detection circuit as claimed in claim 14, wherein each of said non-volatile integrated circuit elements are fuse elements.

Claim 18

A voltage detection circuit as claimed in claim 12, wherein said binary control means includes a plurality of circuit elements that are adapted to be disposed into a predetermined binary state in response to a laser beam being applied thereto.

Claim 19

A voltage detection circuit as claimed in claim 12, wherein said binary control means includes at least two input terminals adapted to be selectively disposed into one of a first and second binary state.

Claim 20

A voltage detection circuit as claimed in claim 1, wherein said voltage converter circuit is adapted to detect said source voltage and includes a linear resistive network coupled to said source voltage for selectively dividing said detected voltage into one of at least two distinct levels defined by said resistive network, said regulation means being coupled to said resistive network for selecting the distinct level of connected voltage to be applied to said comparator means.

Claim 21

A voltage detection circuit as claimed in claim 19, wherein said linear resistive network is a voltage divider network defining a plurality of output terminals, said regulation means including a plurality of switching means, each switching means being coupled intermediate an output terminal of said resistive network and said comparator for selectively coupling each of said output terminals of said resistive network to said comparator to selectively vary the distinct level of the converted voltage applied to said comparator.

Claim 22

A voltage detection circuit as claimed in claim 20, wherein said resistive network is comprised of a plurality of integrated circuit resistors.

Claim 23

A voltage detection circuit as claimed in claim 20, wherein said regulation means includes a binary control means coupled to each of said switching means for digitally selecting one of said switching means to thereby couple said output terminal of said resistive network coupled to said selected switching means to said comparator circuit to apply said converted voltage of a predetermined level thereto.

Claim 24

A voltage detection circuit as claimed in claim 20, wherein said comparator circuit is an operational amplifier formed of a current mirror defining an inverted input and a non-inverted input.

Claim 25

A voltage detection circuit as claimed in claim 22, wherein said binary control means include a plurality of nonvolatile memory integrated circuit elements that are set to a predetermined binary state during fabrication of the circuit element to thereby select the distinct level of the converted voltage to be applied to the comparator circuit at the time that the regulation circuit is integrated into a circuit chip.

Claim 26

A voltage detection circuit as claimed in claim 22, wherein said binary control means includes at least two input terminals adapted to be selectively disposed into one of a first and second binary state.

Claim 27

A voltage detection circuit as claimed in claim 24, wherein each of said non-volatile integrated circuit elements are FAMOS elements.

Claim 28

A voltage detection circuit as claimed in claim 24, wherein each of said non-volatile integrated circuit memory elements are MNOS elements.

Claim 29

A voltage detection circuit as claimed in claim 24, wherein each of said non-volatile memory integrated circuit elementsare fuse elements.

Claim 30

A voltage detection circuit as claimed in claim 24, wherein each of said non-volatile memory elements are adapted to be disposed into a predetermined binary state in response to a laser beam being applied thereto.

Claim 31

A voltage detection circuit as claimed in claim 1, wherein said voltage converter means includes a voltage divider means for linearly dividing said converted voltage and producing a divided voltage representative of the source voltage delivered by said voltage source.

Claim 32

A voltage detection circuit as claimed in claim 30, wherein said voltage converter means includes a voltage follower operational amplifier means having a current mirror defined by at least two N-channel transistors and at least two P-channel transistors having the same conductance coefficients as the aforementioned N-channel and P-channel transistors, respectively, said voltage divider means being coupled to the output of said operational amplifier for producing said converted voltage to be applied to said comparator means in response to the source voltage, said source voltage being applied to said voltage follower operational amplifier means.

Claim 33

A voltage detection circuit comprising a voltage source, said voltage source being adapted to deliver a source voltage, a circuit means for producing an output voltage that is independent of variations in temperature and variations in the source voltage, said circuit means including two like polarity MOS transistors having distinct threshold voltages, said output voltage produced by said circuit means being integrally related to the difference in the threshold voltages of said like polarity MOS transistors, said circuit means defining a reference voltage means for producing a set reference output voltage, voltage converter means for producing a voltage representative of the source voltage delivered by said voltage source, comparator means for receiving said set reference output voltage and said converted voltage and for providing a comparison signal in response thereto, and pulse generating means for coincidentally applying differential sampling pulses having a predetermined time interval to said reference voltage means, voltage converter means and comparator means for selectively energizing each of said reference voltage means, voltage converter means and comparator means for said predetermined time interval that said sampling pulses are applied thereto.

Claim 34

A voltage detection circuit comprising a voltage source, said voltage source being adapted to deliver a source voltage, a circuit means for producing an output voltage that is independent of variations in temperature and variations in the source voltage, said circuit means including two like polarity MOS transistors having distinct threshold voltages, said output voltage produced by said circuit means being integrally related to the difference in the threshold voltages of said like polarity MOS transistors, said circuit means defining a reference voltage means for producing a set reference output voltage, voltage converter means for producing a voltage representative of the source voltage delivered by said voltage source, comparator means for receiving said set reference output voltage and said converted voltage and for providing a comparison signal in response thereto, and pulse generating means for coincidentally applying differential sampling pulses having a predetermined time interval to said reference voltage means, voltage converter means and comparator means for selectively energizing each of said reference voltage means, voltage converter means and comparator means for said predetermined time interval that said sampling pulses are applied thereto.

Claim 35

A voltage detection circuit as claimed in claim 32, and including memory means coupled to said comparator means for storing said comparison signal produced by said comparator means when said sampling pulses are applied to said memory means.

Claim 36

A voltage detection circuit as claimed in claim 32, wherein said pulse generating means includes a flip-flop shift register adapted to receive a first high frequency clock signal and a second lower frequency write-in signal and in response to the leading edge of said clock signal producing a delayed output signal having the same period as the write-in signal and delayed with respect to said write-in signal by a period equal to one-half the period of said clock signal and differential gating means adapted to receive said delayed output signal and said write-in signal and in response thereto produce a differential sampling pulse signal having a duty cycle equal to one-half the period of said high frequency clock signal and occurring once during each half period of said lower frequency write-in signal.

Claim 37

A voltage detection circuit as claimed in claim 32, wherein said reference voltage circuit includes a voltage follower operational amplifier including a current mirror defined by N-channel transistors and P-channel transistors, respectively, and a voltage divider coupled to the output of said operational amplifier for producing said set reference voltage to be applied to said comparator means in response to said reference voltage being applied to said voltage follower operational amlifier means.