Apparatus for converting code signal to visual display

Claim 2

Apparatus for converting a train of signals representative of a code corresponding to a letter, number, or symbol to a visual display of such corresponding letter, number, or symbol, said train of signals being made up of individual signals of at least two distinct time durations, said apparatus comprising: means for producing a clock signal of a preselected time duration for each individual signal in said train of signals; means for resolving the time relation of each of said individual signals in the train of signals to said clock signal, said resolving means including means for producing a first signal if said signal being resolved is less than said clock signal, and a second signal if said signal being resolved is greater than said clock signal; addressor means for receiving said first and second signals produced by said resolving means and storing said signals to generate a given address dependent upon the particular signals and the order said signals are received, said addressor means producing a signal representative of said given address; memory means containing a respective letter, number, or symbol corresponding to each address of said addressor means and receiving said signal from said addressor means representative of said given address, said memory means producing a signal representative of such respective letter, number, or symbol of said given address; sensing means for sensing the end of the train of signals and producing a signal indicative of the end of the train of signals; and display means associated with said memory means and said sensing means for receiving said signal representative of said respective letter, number, or symbol and said signal from said sensing means and producing a visual display of said respective letter, number, or symbol when said sensing means senses the end of said train of signals.

Claim 3

The invention of claim 1 wherein said clock signal producing means includes means for producing a clock signal of variable time duration, and means for selecting a clock signal of particular time duration from said variable time duration clock signal producing means.

Claim 4

The invention of claim 1 further including means for converting said individual signals in said signal train to a given electrical potential level signal, for the duration of time of such individual signal, from a different electrical potential level.

Claim 5

The invention of claim 3 wherein said sensing means includes: means for producing a second clock signal of a time duration greater than said clock signal of preselected time duration when said given level signal is produced; means for receiving said second clock signal and said given level signals; said receiving means producing a signal indicative of the end of a train of signals if a given level signal is not received by the end of said second clock signal.

Claim 6

The invention of claim 4 wherein said second clock signal producing means produces a signal of a time duration equal to at least three times the time duration of said clock signal of preselected time duration.

Claim 7

The invention of claim 3 further including: means associated with said signal converting means for procucing an audio signal corresponding in time duration to any given level signal; and means for detecting errors in such train of signals and producing a signal when an error is detected, for inhibiting said audio signal clearing said given address from said addressor means, and producing a visual indication that an error has been detected.

Claim 8

The invention of claim 6 wherein said error detecting means is associated with said sensing means and said signal converting means whereby, after the end of a train of signals is sensed by said sensing means, when said converting means receives a subsequent individual signal, said error detecting means is reset.

Claim 9

The invention of claim 1 wherein said addressor means is a universal bidirectional shift register, and wherein said resolving means includes means for resolving the time relation of the first signal in said train of signals and producing a signal to set the shift direction of said shift register.

Claim 10

The invention of claim 8 wherein said resolving means further includes means for parallel loading said shift register with said signal from said first signal resolving means; second signal resolving means for determining the time relation of subsequent signals in said train of signals and producing signals representative of such determination; and means for loading said shift register with said last mentioned signals in the direction set by said first signal resolving means.

Claim 11

Apparatus for converting an International Morse Code signal pattern representative of a letter, number, or symbol to a visual display of such letter, number, or symbol, said signal pattern being made up of individual dot and dash signals, said dash signals being of a dime duration substantially longer than the time duration of said dot signals, said apparatus comprising: means for producing a first adjustable time length clock signal for each individual signal of said signal pattern, said first clock signal being preset to be of a time duration between that of said dot and dash signals; first resolving means for resolving the time relation of the first signal of said individual dot and dash signals of said signal pattern to said first clock signal, said first resolving means producing a first signal representative of said first individual signal being a dot signal, and producing a second signal representative of said first individual signal being a dash signal; second resolving means for resolving the time relation of subsequent signals of said individual dot and dash signals of said signal pattern to said first clock signal, said second resolving means producing first signals representative of said subsequent signals being dot signals, and second signals representative of said subsequent signals being dash signals; a universal bidirectional shift register associated with said first and second resolving means for receiving said first or second signal from said first resolving means to load said first or second signal in said shift register and to set the direction that said shift register will shift upon receiving said first and second signals from said second resolving means, and receiving said first and second signals from said second resolving means to generate a given address dependent upon said first and second signals and the order in which they are received, said shift register producing a signal representative of said given address; memory means for containing a respective letter, number, or symbol corresponding to each address of said addressor means and receiving said signal from said shift register of said given address, said memory means producing a signal representative of such respective letter, number, or symbol of said given address; means for sensing the end of said signal pattern including means for producing a second adjustable time length clock signal for each individual signal of said signal pattern, said second clock signal being preset to be of a time relation substantially greater than said first clock signal, means for receiving said second clock signal and said signals of said signal pattern, said receiving means producing a signal indicative of the end of said signal pattern when no signal from said signal pattern is received by the end of said second clock signal; and display means, associated with said memory means and said sensing means, for receiving said signal representative of said respective letter, number, and said signal from said receiving means and producing a visual display of said respective letter, number, or symbol when said sensing means senses the end of said signal pattern.

Claim 12

Apparatus for converting an International Morse Code signal pattern representative of a letter, number, or symbol to a visual display of such letter, number, or symbol, said signal pattern being made up of individual dot and dash signals, said dash signals being of a dime duration substantially longer than the time duration of said dot signals, said apparatus comprising: means for producing a first adjustable time length clock signal for each individual signal of said signal pattern, said first clock signal being preset to be of a time duration between that of said dot and dash signals; first resolving means for resolving the time relation of the first signal of said individual dot and dash signals of said signal pattern to said first clock signal, said first resolving means producing a first signal representative of said first individual signal being a dot signal, and producing a second signal representative of said first individual signal being a dash signal; second resolving means for resolving the time relation of subsequent signals of said individual dot and dash signals of said signal pattern to said first clock signal, said second resolving means producing first signals representative of said subsequent signals being dot signals, and second signals representative of said subsequent signals being dash signals; a universal bidirectional shift register associated with said first and second resolving means for receiving said first or second signal from said first resolving means to load said first or second signal in said shift register and to set the direction that said shift register will shift upon receiving said first and second signals from said second resolving means, and receiving said first and second signals from said second resolving means to generate a given address dependent upon said first and second signals and the order in which they are received, said shift register producing a signal representative of said given address; memory means for containing a respective letter, number, or symbol corresponding to each address of said addressor means and receiving said signal from said shift register of said given address, said memory means producing a signal representative of such respective letter, number, or symbol of said given address; means for sensing the end of said signal pattern including means for producing a second adjustable time length clock signal for each individual signal of said signal pattern, said second clock signal being preset to be of a time relation substantially greater than said first clock signal, means for receiving said second clock signal and said signals of said signal pattern, said receiving means producing a signal indicative of the end of said signal pattern when no signal from said signal pattern is received by the end of said second clock signal; and display means, associated with said memory means and said sensing means, for receiving said signal representative of said respective letter, number, and said signal from said receiving means and producing a visual display of said respective letter, number, or symbol when said sensing means senses the end of said signal pattern.

Claim 13

The invention of claim 10 wherein said second clock signal is of a time duration substantially equal to three times the time duration of said first clock signal.

Claim 14

The invention of claim 11 further including means associated with said bidirectional shift register for setting the level of said first and second signals produced by said first and second resolving means to first and second levels dependent upon said first individual signal of said signal pattern, whereby when said first individual signal is resolved by said first resolving means to be of a time duration less than said first clock signal, said signal representative of said first individual signal and all signals of like time duration are entered into said shift register in one direction at said first level and all signals representative of said other time duration enter said shift register in said one direction at said second level and when the said first individual signal is resolved by said first resolving means to be of a time duration greater than said first clock signal, said signal representative of said first signal and all signals of like time duration are entered into said shift register in the opposite direction at said first level, and all signals representative of said other time duration enter said shift register in said opposite direction at said second level.