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Patent US4254471A successfully refreshed from Google Patents.
US4254471A
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Binary adder circuit
Assignee: CAMBRIDGE PARALLEL PROCESSING Ltd
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Filing: 1979-03-12
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Granted: 1981-03-03
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Expires: 1999-03-12
Abstract
Abstract A binary adder circuit which, in response to a mode selection signal, is forced to operate as if two of its inputs were equal, irrespective of the actual value of those inputs. In this condition, the circuit acts effectively as a connector, coupling two of its inputs direct to the sum and carry outputs. The invention is useful in a circuit arrangement for performing adding and shifting operations.
Inventors
- 👤 David J. Hunt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:13
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F7/502; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3868
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
217 words
A binary adder circuit having three inputs and sum and carry outputs, comprising: (a) an equivalence circuit connected to the first and second inputs for producing a control signal having a first value when those inputs are equal and a second value when they are not equal; (b) first circuit means, connected to the third input and responsive to the control signal, for producing a sum signal equal to the third input when the control signal has its first value and equal to the inverse of the third input when the control signal has its second value, the sum signal being applied to the sum output; (c) second circuit means, connected to the three inputs and responsive to the control signal, for producing a carry signal equal to either of the first and second inputs when the control signal has its first value and equal to the third input when the control signal has its second value, the carry signal being applied to the carry output; and (d) means operative in response to a mode control signal for forcing the control signal to its first value irrespective of the values of the first and second inputs, thereby making the sum output equal to the third input and the carry output equal to the first or second input.
Claim 2
Dependent Claim
217 words
A binary adder circuit having three inputs and sum and carry outputs, comprising: (a) an equivalence circuit connected to the first and second inputs for producing a control signal having a first value when those inputs are equal and a second value when they are not equal; (b) first circuit means, connected to the third input and responsive to the control signal, for producing a sum signal equal to the third input when the control signal has its first value and equal to the inverse of the third input when the control signal has its second value, the sum signal being applied to the sum output; (c) second circuit means, connected to the three inputs and responsive to the control signal, for producing a carry signal equal to either of the first and second inputs when the control signal has its first value and equal to the third input when the control signal has its second value, the carry signal being applied to the carry output; and (d) means operative in response to a mode control signal for forcing the control signal to its first value irrespective of the values of the first and second inputs, thereby making the sum output equal to the third input and the carry output equal to the first or second input.
Claim 3
Dependent Claim
76 words
An information processing arrangement comprising a series of binary adder circuits in accordance with claim 1, each adder circuit having first and second single-bit registers connected to its first and second inputs respectively, means for connecting the sum output of each adder circuit to the input of the first register associated with it, and means for connecting the carry output of each adder circuit to the third input of the next adder circuit in the series.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-03-02 | 1984-09-01 | 1985-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-03-02 | 1988-09-01 | 1989-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-03-02 | 1992-09-01 | 1993-03-03 | $7700.00 | Window Closed / Lapsed |