Patent US4253196A successfully refreshed from Google Patents.
US4253196A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency converter, as for first detector of heterodyne radio receiver
Assignee: RCA Licensing Corp
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Filing: 1980-01-15
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Granted: 1981-02-24
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Expires: 2000-01-15
Abstract
Abstract A frequency converter including a first pair of transistors with an interconnection between their emitters for receiving a unidirectional current with signal variations to be converted, at least one of their collectors arranged to supply converted signal currents. A second pair of transistors with an interconnection between their emitter electrodes connected by resistor to reference potential is connected to regenerate oscillations in a tank circuit. One of these transistors has its collector connected to the tank circuit; the other has its base connected to receive scaled-down oscillations from the tank circuit and has its collector provided with a resistive load to develop switching signal to be applied between the base electrodes of the first pair of transistors. Appropriate scaling of the resistive load to the emitter resistor shared by second pair of transistors results in maximum conversion efficiency.
Inventors
- 👤 Max E. Malchow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 14:00
CPC Classifications
H; H03; H03D; H03D7/00; H03D7/12
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
355 words
Frequency conversion circuitry comprising: first, second, third and fourth transistors of the same conductivity type, each having an input electrode and having common and output electrodes defining the ends of its principal current conduction path, the conductivity of which is controlled responsive to the potential between its common and input electrodes; first and second terminals for application of reference and operating voltages, respectively; a third terminal for application of a first biasing voltage intermediate to said reference and operating voltages, which third terminal connects to the input electrode of said first transistor; a fourth terminal for application of a second biasing voltage intermediate to said reference and first biasing voltages, which fourth terminal connects to the input electrode of said third transistor. means, responsive to an input frequency to be converted, for applying to an interconnection between the common electrodes of said first and second transistors, a unidirectional current of a polarity tending to cause them to conduct current; respective means connecting the output electrodes of said first and second transistors to said second terminal, at least one of which includes load means for receiving converted input signal; first resistive means with a first end connected to said first terminal and with a second end connected to an interconnection between the common electrodes of said third and fourth transistors; means providing regenerative feedback connection from the output electrode of said third transistor to the input electrode of said fourth transistor for generating local oscillations that switch the third and fourth transistors into alternate conduction; and second resistive means with a first end connected to said second terminal, with a second end to which the output electrode of said fourth transistor connects, and of a resistance respective to that of said first resistive means such that local oscillator output voltage appearing at its second end responsive to alternate conduction of said fourth transistor, which local oscillator output voltage is applied to the input electrode of said second transistor, results in alternate conduction of said first and second transistors with each conducting for a substantially 50% duty cycle, 50% duty cycle being associated with maximum conversion efficiency.
Claim 2
Dependent Claim
355 words
Frequency conversion circuitry comprising: first, second, third and fourth transistors of the same conductivity type, each having an input electrode and having common and output electrodes defining the ends of its principal current conduction path, the conductivity of which is controlled responsive to the potential between its common and input electrodes; first and second terminals for application of reference and operating voltages, respectively; a third terminal for application of a first biasing voltage intermediate to said reference and operating voltages, which third terminal connects to the input electrode of said first transistor; a fourth terminal for application of a second biasing voltage intermediate to said reference and first biasing voltages, which fourth terminal connects to the input electrode of said third transistor. means, responsive to an input frequency to be converted, for applying to an interconnection between the common electrodes of said first and second transistors, a unidirectional current of a polarity tending to cause them to conduct current; respective means connecting the output electrodes of said first and second transistors to said second terminal, at least one of which includes load means for receiving converted input signal; first resistive means with a first end connected to said first terminal and with a second end connected to an interconnection between the common electrodes of said third and fourth transistors; means providing regenerative feedback connection from the output electrode of said third transistor to the input electrode of said fourth transistor for generating local oscillations that switch the third and fourth transistors into alternate conduction; and second resistive means with a first end connected to said second terminal, with a second end to which the output electrode of said fourth transistor connects, and of a resistance respective to that of said first resistive means such that local oscillator output voltage appearing at its second end responsive to alternate conduction of said fourth transistor, which local oscillator output voltage is applied to the input electrode of said second transistor, results in alternate conduction of said first and second transistors with each conducting for a substantially 50% duty cycle, 50% duty cycle being associated with maximum conversion efficiency.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-02-24 | 1984-08-25 | 1985-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-02-24 | 1988-08-25 | 1989-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-02-24 | 1992-08-25 | 1993-02-24 | $7700.00 | Window Closed / Lapsed |