Programmable sequence controller with counting function

Claim 1

A programmable sequence controller comprising: memory means for storing a sequence of control instructions identified respectively by memory addresses thereof, each of said instructions including an operation command and address data, wherein said operation commands include test and output commands; read-out control means for controlling said memory means so as to successively read out said control instructions therefrom; an input circuit operatively connected to a plurality of addressable external input devices for converting states of said external input devices into logical values; an output circuit operatively connected to a plurality of addressable external output devices; an addressable latch circuit including at least one flip flop, said flip flop having a set output terminal; a counter having a count-up terminal connected to the set output terminal of said flip flop, the content of said counter being changed by one each time said flip flop is set; setting means for manually setting the count-up value of said counter; means for comparing the content of said counter with the count-up value set in said setting means and for generating a count-up value signal when the content of said counter coincides with the count-up value set in said setting means; addressable means connected to said comparing means to receive the count-up value signal for supplying a logical value indicative of the status of said comparing means; and logic operation means connected to said memory means, said input circuit, said addressable means and said output circuit, and responsive to the test command of a first instruction for testing a logical value of one of said external input devices and a logical value of said addressable means specified by the address data of the first instruction, and also responsive to an output command of a second instruction for generating an output command signal based upon the result of the test; said output circuit being operable to energize or deenergize one of said addressed external output devices designated by the address data in the second instruction in response to said output command signal from said logic operation means; and said flip flop being set in response to said output command signal generated from said logic operation means when said flip flop is designated by the address data in the second instruction.