US4176403A
Expired / Lapsed
US
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Programmable sequence controller
Assignee: Toyoda Koki KK
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Filing: 1978-06-20
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Granted: 1979-11-27
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Expires: 1998-06-20
Abstract
Abstract A programmable sequence controller wherein in accordance with a sequence program read out from a memory, a logic operation circuit tests a logical value supplied from an input converter connected to an external input element and generates an output command signal based upon the result of the test. The output command signal is stored in an output memory which has two storage addresses for each external output element, each storage address corresponding to a particular memory storage element addressed by the sequence program. A gate circuit is connected to these two memory storage elements and inhibits the application of an output command signal from one of the memory storage elements to an output converter when the gate circuit receives a logical value from the input converter. When receiving an output command signal from the other of the two memory storage elements the gate circuit then applies this signal to the output converter. Thus, an output element connected to the output converter is energized immediately in response to the operation of an input element.
Inventors
- 👤 Isao Suzuki
- 👤 Toshihiko Yomogida
- 👤 Tsuyoshi Yokota
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:51
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G05B19/054; G05B2219/00; G05B2219/10; G05B2219/11; G05B2219/1125; G05B2219/1174
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
293 words
A programmable sequence controller comprising: memory means for storing a sequence of control instructions, each of said instructions including an operation command and address data associated with said operation command, wherein said operation commands include test commands or output commands; read-out control means for controlling said memory means so as to successively read out each control instruction in said sequence of control instructions therefrom; at least one input converter connectable to an external input element for converting an operational state thereof into a logical value; a data selector connected to said input converter and responsive to said address data for selecting said logical value of said input element when the input element is designated by said address data; logic operation means responsive to a said test command for testing said selected logical value supplied from said data selector and thereafter responsive to a said output command for generating an output command signal based upon the result of the test; an addressable output memory having at least two storage locations and adapted to store said output command signal at each of said two storage locations as designated by said address data associated with said output command; gate means connected to said input converter and said two storage locations for inhibiting passage of said output command signal from one of said two storage locations when receiving said logical value of said input element and for enabling passage of said output command signal from the one of said two storage locations when receiving said output command signal from the other of said two storage locations; and at least one output converter connectable to an external output element and connected to said gate means for energizing said output element based upon said output command signal supplied therefrom.
Claim 2
Dependent Claim
293 words
A programmable sequence controller comprising: memory means for storing a sequence of control instructions, each of said instructions including an operation command and address data associated with said operation command, wherein said operation commands include test commands or output commands; read-out control means for controlling said memory means so as to successively read out each control instruction in said sequence of control instructions therefrom; at least one input converter connectable to an external input element for converting an operational state thereof into a logical value; a data selector connected to said input converter and responsive to said address data for selecting said logical value of said input element when the input element is designated by said address data; logic operation means responsive to a said test command for testing said selected logical value supplied from said data selector and thereafter responsive to a said output command for generating an output command signal based upon the result of the test; an addressable output memory having at least two storage locations and adapted to store said output command signal at each of said two storage locations as designated by said address data associated with said output command; gate means connected to said input converter and said two storage locations for inhibiting passage of said output command signal from one of said two storage locations when receiving said logical value of said input element and for enabling passage of said output command signal from the one of said two storage locations when receiving said output command signal from the other of said two storage locations; and at least one output converter connectable to an external output element and connected to said gate means for energizing said output element based upon said output command signal supplied therefrom.
Claim 3
Dependent Claim
42 words
A programmable sequence controller as set forth in claim 1, wherein: said input converter, said data selector, said addressable output memory, said gate means and said output converter are provided on a circuit board so as to constitute as input/output hybrid card.
Claim 4
Dependent Claim
55 words
A programmable sequence controller as set forth in claim 2, wherein: said data selector is also connected to said two storage locations of said addressable output memory for selecting said output command signal stored at each of said two locations when said data selector receives said address data designating said each of two storage locations.
Claim 5
Dependent Claim
114 words
A programmable sequence controller as set forth in claim 2, wherein said gate means comprises: first signal outputting means connected to said input converter and said other of said two storage locations for outputting a gate signal when not receiving said logical value from said input converter and when receiving said output command signal from said other of said two storage locations; and second signal outputting means connected to said first signal outputting means, said one of said two storage locations and said output converter for outputting said output command signal from said one of said two storage locations to said output converter when receiving said gate signal from said first signal generating means.
Claim 6
Dependent Claim
70 words
A programmable sequence controller as claimed in claim 4, wherein: said first signal outputting means comprises an inverter connected to said input converter and an OR gate connected to the other of said two storage locations and said inverter; and said second signal outputting means is an AND gate responsive to said gate signal from said OR gate and said output command signal from said one of two storage locations.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-11-26 | 1983-05-28 | 1983-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-11-26 | 1987-05-28 | 1987-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-11-26 | 1991-05-28 | 1991-11-27 | $7700.00 | Window Closed / Lapsed |