US4011544A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Control system having a programmed logic unit
Assignee: Alcatel CIT SA
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Filing: 1974-12-13
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Granted: 1977-03-08
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Expires: 1994-12-13
Abstract
Abstract Programmed logic control system intended for the monitoring of a set of elements, more particularly a switching exchange comprising an addressable memory containing the list of orders enabling the said monitoring, input detectors receiving the data concerning the state of the various controlled elements, registers for storing the data used by the program, output means enabling the sending, towards the elements, of orders for the changing of state and/or digital data contained in the registers and means for addressing the memory effecting an analysis according to a logic unit comprising several states of the input data.
Inventors
- 👤 Antoine Cherrey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:53
CPC Classifications
H; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/54; H04Q3/545; H04Q3/54575; H04Q3/54591
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
276 words
Logic control system intended for controlling a set of elements by transmitting data and orders to the set of elements, more particularly for use in a telecommunication exchange, comprising: a directly addressable memory and associated addressing means, a set of input detectors receiving data concerning the state of the said elements, a set of registers for storing said data to be transmitted to said set of elements to be controlled, and output means connected to said set of registers and receiving as inputs the data stored in said registers for sending to said elements orders and data, said memory being composed of addressable lines, each containing a line number and a coded instruction word, which is sent to the said addressing means and output means, and the said addressing means comprising: an address register connected to said memory, an adder having its output connected to said address register and one of its inputs connected to said memory, said adder receiving as one input a line number from said memory, a validation circuit, whose inputs are connected to the outputs of the said detectors, and controlled by instruction words each allowing the selection of at least one input detector, a coder, whose inputs are connected to the outputs of the validation circuit and delivering at its output a binary number to said adder to be added to said line number supplied to said adder from said memory in order to obtain the address of the next line to be read in the memory, said binary number from said coder corresponding to the address increment to said address of the next line to be read in the memory.
Claim 2
Dependent Claim
276 words
Logic control system intended for controlling a set of elements by transmitting data and orders to the set of elements, more particularly for use in a telecommunication exchange, comprising: a directly addressable memory and associated addressing means, a set of input detectors receiving data concerning the state of the said elements, a set of registers for storing said data to be transmitted to said set of elements to be controlled, and output means connected to said set of registers and receiving as inputs the data stored in said registers for sending to said elements orders and data, said memory being composed of addressable lines, each containing a line number and a coded instruction word, which is sent to the said addressing means and output means, and the said addressing means comprising: an address register connected to said memory, an adder having its output connected to said address register and one of its inputs connected to said memory, said adder receiving as one input a line number from said memory, a validation circuit, whose inputs are connected to the outputs of the said detectors, and controlled by instruction words each allowing the selection of at least one input detector, a coder, whose inputs are connected to the outputs of the validation circuit and delivering at its output a binary number to said adder to be added to said line number supplied to said adder from said memory in order to obtain the address of the next line to be read in the memory, said binary number from said coder corresponding to the address increment to said address of the next line to be read in the memory.
Claim 3
Dependent Claim
88 words
Control system according to claim 1, in which the said output means comprise a first order decoder connected to the output of said memory and an order generator connected to the output of said first order decoder, said order generator comprising flip-flops controlled by instruction words from said memory via said first order decoder, and each transmitting an order in the form of an electric polarity, said instruction words being received by said first order decoder the outputs of which are connected to the inputs of said flip-flops.
Claim 4
Dependent Claim
83 words
Control system according to claim 2, further comprising a second order decoder connected to the output of said memory and a time delay device using a counter, said delay device being connected up to said second order decoder and to said validation circuit for enabling the addressing in the memory of the same line number throughout the whole duration of the time delay, the duration of the time delay being determined by the order transmitted by the second order decoder to said counter.
Claim 5
Dependent Claim
78 words
Control system according to claim 2 wherein said output means further comprises at least one gate and a distributor said gate and distributor being controlled by the outputs of said first order generator wherein said gate is connected between an element to be controlled and a corresponding register of said set of registers, and wherein said distributor is connected between several of said elements to be controlled and a plurality of the registers of said set of registers.
Claim 6
Dependent Claim
69 words
Control system according to claim 2 wherein said output means further comprises at least one gate and at least one comparator, said gate being controlled by the outputs of said order generator, said comparator being connected to receive as inputs the input of a selected register and the output of a selected register, said gate being connected between an element to be controlled and the output of said comparator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-03-07 | 1980-09-06 | 1981-03-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-03-07 | 1984-09-06 | 1985-03-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-03-07 | 1988-09-06 | 1989-03-08 | $7700.00 | Window Closed / Lapsed |