Fault detection apparatus for a programmable controller

Claim 2

An improved programmable controller of the type having a controller processor, a memory with a terminal to be monitored and an I/O interface rack connected to one another through an I/O data bus, the controller processor being operable to couple input/output data between an I/O image table in the memory and the I/O interface rack through execution of an I/O routine, wherein the improvement comprises: sensing circuit means electrically connected to the memory terminal for generating a bit of data to the controller processor in response to a fault at the memory terminal; fault indicating means coupled to the memory through the I/O data bus, for receiving fault status bits that are output from the I/O image table during the I/O routine; wherein the controller processor is connected to the sensing circuit means and is operable to couple fault status bits from the sensing circuit means to the I/O image table; and wherein the controller processor couples fault status bits to the fault indicating means through execution of the I/O routine.

Claim 3

In the programmable controller of claim 1, wherein the terminal on the memory is a power supply input adapted for connection to a memory back-up battery,, the further improvement circuit means includes a circuit with an input electrically connected to the power supply input on the memory and with an output connected to the controller processor, this circuit being operable to detect an undervoltage condition in the back-up battery.

Claim 4

The improvement recited in claim 1, wherein the fault indicating means is mounted on the I/O interface rack.

Claim 5

The improvement recited in claim 1, wherein the fault indicating means includes a device which emits a visible fault signal in response to receiving a fault status bit signal.

Claim 6

The improvement recited in claim 1, wherein the fault indicating means includes a device which emits an audible fault signal in response to receiving a fault status bit signal.

Claim 7

The improvement recited in claim 1, further comprising program panel means coupled to the controller processor means for displaying the I/O address of the fault status bit.

Claim 8

A programmable controller for sensing a weak memory back-up battery, which is adapted to be connected to a power supply input on a memory means, and which is used to power a portion of the memory means when the controller is disconnected from its primary power source, the controller comprising: an I/O interface rack adapted to be connected to input devices and output devices on a machine; the memory means, for storing an I/O image table of data that corresponds to the status of the input devices and output devices on the machine, and for storing two groups of processor instructions; a controller processor coupled to the memory means and coupled to the I/O interface rack, the controller processor being operable to read and execute the first group of processor instructions in the memory means to periodically couple data between the memory means and the I/O interface rack during an I/O scan; sensing circuit means, with an input connected to the power supply input on the memory means and with an output coupled to the controller processor, for generating fault status bits to the controller processor in response to an insufficient signal at the power supply input; and fault indicating means disposed on the I/O interface rack and coupled to both the controller processor and the memory means, for receiving fault status bits; wherein the controller processor is responsive to read and execute the second group of processor instructions in the memory means to couple fault status bits from the sensing circuit means to the I/O image table in the memory means, and is responsive to the first group of processor instructions to output these fault status bits to the fault status indicating means during the next I/O scan.

Claim 9

A programmable controller for sensing a weak memory back-up battery, which is adapted to be connected to a power supply input on a memory means, and which is used to power a portion of the memory means when the controller is disconnected from its primary power source, the controller comprising: an I/O interface rack adapted to be connected to input devices and output devices on a machine; the memory means, for storing an I/O image table of data that corresponds to the status of the input devices and output devices on the machine, and for storing two groups of processor instructions; a controller processor coupled to the memory means and coupled to the I/O interface rack, the controller processor being operable to read and execute the first group of processor instructions in the memory means to periodically couple data between the memory means and the I/O interface rack during an I/O scan; sensing circuit means, with an input connected to the power supply input on the memory means and with an output coupled to the controller processor, for generating fault status bits to the controller processor in response to an insufficient signal at the power supply input; and fault indicating means disposed on the I/O interface rack and coupled to both the controller processor and the memory means, for receiving fault status bits; wherein the controller processor is responsive to read and execute the second group of processor instructions in the memory means to couple fault status bits from the sensing circuit means to the I/O image table in the memory means, and is responsive to the first group of processor instructions to output these fault status bits to the fault status indicating means during the next I/O scan.

Claim 10

The programmable controller of claim 7, wherein the fault indicating means includes a device which emits a visible fault signal in response to the receiving a fault status bit signal.

Claim 11

The programmable controller of claim 7, wherein the fault indicating means includes a device which emits an audible fault signal in response to receiving a fault status bit signal.

Claim 12

The programmable controller of claim 7, wherein the sensing circuit means is responsive to both an undervoltage fault in the memory back-up battery and an I/O communication fault and generates a respective fault status bit for each fault.