US4250407A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi function patch pin circuit
Assignee: Gemalto Terminals Ltd
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Filing: 1977-11-23
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Granted: 1981-02-10
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Expires: 1997-11-23
Abstract
Abstract A single patch on an integrated circuit is arranged to patch any one of four different logical states into the circuit, according to whether the pin is grounded, floating, coupled to a supply rail via a resistor, or coupled to the supply rail directly. In one embodiment, the voltage thresholds of three transistors are arranged so that they switch on successively in response to successively higher voltages on the patch pin, thereby controlling the binary logic signals at each of two output points in the circuit; in the other embodiment, multi-emitter transistors are arranged with differing current thresholds to achieve the same result.
Inventors
- 👤 Howard A. Dorey
- 👤 Edward A. Martin
- 👤 Michael I. Spooner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:54
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/415; H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806; H03K19/02; H03K19/08; H03K19/0813; H03K19/082; H03K19/0823
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
243 words
An integrated circuit having external pins including at least one patch pin arranged to receive a patching signal to patch data into said circuit and two further pins arranged to be coupled to respective voltage supply rails; and internal circuit means comprising an input, means coupling said input to said patch pin, first and second outputs, means for establishing a first predetermined operative level at said input in the absence of connection to said patch pin, and a plurality of interconnected semiconductor devices having respective predetermined first, second and third operative thresholds which are intermediate two respective operative levels each established at said input by coupling of said patch pin to a respective one of said supply rails, said first threshold being the closest of said thresholds to one of said two operative levels, said second threshold being the closest of said thresholds to the other of said two operative levels, and said third threshold being between said first and second thresholds and also being the only one of said thresholds between said first predetermined operative level and a second predetermined operative level established at said input by connection of said patch pin via resistance means to a predetermined one of said supply rails, said semiconductor devices coupling said input to said outputs such that, for each of said operative levels established at said input as aforesaid, said circuit means supplies a respective and different combination of binary digit levels at said outputs.
Claim 2
Dependent Claim
243 words
An integrated circuit having external pins including at least one patch pin arranged to receive a patching signal to patch data into said circuit and two further pins arranged to be coupled to respective voltage supply rails; and internal circuit means comprising an input, means coupling said input to said patch pin, first and second outputs, means for establishing a first predetermined operative level at said input in the absence of connection to said patch pin, and a plurality of interconnected semiconductor devices having respective predetermined first, second and third operative thresholds which are intermediate two respective operative levels each established at said input by coupling of said patch pin to a respective one of said supply rails, said first threshold being the closest of said thresholds to one of said two operative levels, said second threshold being the closest of said thresholds to the other of said two operative levels, and said third threshold being between said first and second thresholds and also being the only one of said thresholds between said first predetermined operative level and a second predetermined operative level established at said input by connection of said patch pin via resistance means to a predetermined one of said supply rails, said semiconductor devices coupling said input to said outputs such that, for each of said operative levels established at said input as aforesaid, said circuit means supplies a respective and different combination of binary digit levels at said outputs.
Claim 3
Dependent Claim
15 words
An integrated circuit according to claim 1, wherein the semiconductor devices have different voltage thresholds.
Claim 4
Dependent Claim
15 words
An integrated circuit according to claim 1, wherein the semiconductor devices have different current thresholds.
Claim 5
Dependent Claim
82 words
An integrated circuit according to claim 1, in combination with a plurality of pins to which said patch pin is selectively connectible, a first of said pins being at ground potential, a second of said pins being at a floating potential, a third of said pins being coupled to said predetermined voltage supply rail via resistance means, and a fourth of said pins being coupled to said predetermined voltage supply rail directly, the other of said supply rails being at ground potential.
Claim 6
Dependent Claim
160 words
An integrated circuit having external pins including at least one patch pin arranged to receive a patching signal to patch data into said circuit; and internal circuit means comprising an input, means coupling said input to said patch pin, first, second and third interconnected semi-conductor devices having respective and different predetermined operative thresholds and responsive to the voltage at said input such that, for each of four different voltage levels applied to said patch pin, said first device supplies respective binary digit levels A, B, B and B, said second device supplies respective binary digit levels A, A, B and B, and said third device supplies respective binary digit levels A, A, A and B, and logical circuit means responsive to said first and third devices to combine the respective binary digit levels A, B, B and B with the respective binary digit levels A, A, A and B to form respective binary digit levels A, B, B and A.
Claim 7
Dependent Claim
160 words
An integrated circuit having external pins including at least one patch pin arranged to receive a patching signal to patch data into said circuit; and internal circuit means comprising an input, means coupling said input to said patch pin, first, second and third interconnected semi-conductor devices having respective and different predetermined operative thresholds and responsive to the voltage at said input such that, for each of four different voltage levels applied to said patch pin, said first device supplies respective binary digit levels A, B, B and B, said second device supplies respective binary digit levels A, A, B and B, and said third device supplies respective binary digit levels A, A, A and B, and logical circuit means responsive to said first and third devices to combine the respective binary digit levels A, B, B and B with the respective binary digit levels A, A, A and B to form respective binary digit levels A, B, B and A.
Claim 8
Dependent Claim
21 words
An integrated circuit according to claim 5, wherein said operative thresholds of said first to third devices are in ascending series.
Claim 9
Dependent Claim
44 words
An integrated circuit according to claim 5, wherein the logical circuit means comprises inverter means responsive to said first device to invert the digit levels therefrom, and OR-function means responsive to said inverter means and said third device to combine the digit levels therefrom.
Claim 10
Dependent Claim
15 words
An integrated circuit according to claim 5, wherein said devices are transistors in common-emitter configuration.
References Cited (Backward Citations)
US3207922A
Cited
US3155845A
Cited
GB1250778A
Cited
GB1289799A
Cited
US3609411A
Cited
US3660678A
Cited
US3660677A
Cited
US3671763A
Cited
SU516195A1
Cited
US3969633A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-02-10 | 1984-08-11 | 1985-02-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-02-10 | 1988-08-11 | 1989-02-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-02-10 | 1992-08-11 | 1993-02-10 | $7700.00 | Window Closed / Lapsed |