US4249091A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic circuit
Assignee: Hitachi Ltd
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Filing: 1978-09-06
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Granted: 1981-02-03
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Expires: 1998-09-06
Abstract
Abstract A current mode logic circuit (CML) consisting of emitter-coupled transistors, one acting as a reference element and the other as an input element, a regulation transistor for regulating the emitter current of the transistors, a biasing circuit composed of a diode, a Schottky diode and a resistance element connected in series between a V EE terminal and a V CC terminal and a biasing transistor, the collector of the biasing transistor being connected through a resistor to V CC and connected to the base of the reference transistor, the emitter of which being connected through a resistor to V EE , the bases of the regulation transistor and the biasing transistor being connected to the point between the resistance element and the Schottky diode, so that the emitter current of the transistors and the reference voltage are automatically regulated, whereby CML maintains both the output levels and the input threshold level almost invariant irrespective of changes of transistor characteristics due to temperature and changes in supply voltage, to provide a circuit which is capable of operating on low-power potential and low-amplitude input signal.
Inventors
- 👤 Akira Yamagiwa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:09
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
85 words
A logic circuit including emitter-coupled transistors, the base of one of which being supplied with an input signal, the base of the other being served with a voltage; a regulation transistor for regulating the emitter current of said coupled transistors, a biasing means having a series connection of a junction diode and a Schottky diode, said means generating a predetermined voltage between the emitter and the base of said regulation transistor; and an output terminal being coupled to at least one collector of the transistors.
Claim 2
Dependent Claim
85 words
A logic circuit including emitter-coupled transistors, the base of one of which being supplied with an input signal, the base of the other being served with a voltage; a regulation transistor for regulating the emitter current of said coupled transistors, a biasing means having a series connection of a junction diode and a Schottky diode, said means generating a predetermined voltage between the emitter and the base of said regulation transistor; and an output terminal being coupled to at least one collector of the transistors.
Claim 3
Dependent Claim
86 words
A logic circuit including emitter-coupled transistors, the base of one of which being supplied with an input signal, the base of the other being served with a reference voltage; a regulation transistor for regulating the emitter current of said emitter-coupled transistors; a biasing means having a series connection of a junction diode and; a Schottky diode, said means generating a predetermined voltage between the emitter and the base of the regulation transistor; and an output terminal being coupled to at least one collector of the transistors.
Claim 4
Dependent Claim
86 words
A logic circuit including emitter-coupled transistors, the base of one of which being supplied with an input signal, the base of the other being served with a reference voltage; a regulation transistor for regulating the emitter current of said emitter-coupled transistors; a biasing means having a series connection of a junction diode and; a Schottky diode, said means generating a predetermined voltage between the emitter and the base of the regulation transistor; and an output terminal being coupled to at least one collector of the transistors.
Claim 5
Dependent Claim
22 words
A logic circuit as set forth in claim 2, wherein said regulation transistor is coupled to the emitters of said emitter-coupled transistors.
Claim 6
Dependent Claim
110 words
A current switch circuit comprising; an input transistor being supplied with input signals through the base thereof; a reference transistor being served with a reference voltage through the base thereof, the emitter thereof being connected to the emitter of said input transistor; a regulation transistor connected in common to the emitters of said input and reference transistors for regulating the emitter currents; a biasing means having a series connection of a junction diode and a Schottky diode, said means generating a predetermined voltage between the emitter and the base of the regulation transistor; and an output terminal being coupled to at least one collector of said input and reference transistors.
Claim 7
Dependent Claim
110 words
A current switch circuit comprising; an input transistor being supplied with input signals through the base thereof; a reference transistor being served with a reference voltage through the base thereof, the emitter thereof being connected to the emitter of said input transistor; a regulation transistor connected in common to the emitters of said input and reference transistors for regulating the emitter currents; a biasing means having a series connection of a junction diode and a Schottky diode, said means generating a predetermined voltage between the emitter and the base of the regulation transistor; and an output terminal being coupled to at least one collector of said input and reference transistors.
Claim 8
Dependent Claim
118 words
A current mode logic circuit comprising; an input transistor being supplied with input signals through the base thereof; a reference transistor being provided with a reference voltage through the base thereof, the emitter thereof being connected to the emitter of said input transistor; a regulation transistor connected in common to the emitters of said input and reference transistors for regulating the emitter currents; a resistor connected to the emitter of said regulation transistor; a biasing means having a series connection of a junction diode and a Schottky diode connected in parallel between the base of said regulation transistor and said resistor; and an output terminal being coupled to at least one collector of said input and reference transistors.
Claim 9
Dependent Claim
118 words
A current mode logic circuit comprising; an input transistor being supplied with input signals through the base thereof; a reference transistor being provided with a reference voltage through the base thereof, the emitter thereof being connected to the emitter of said input transistor; a regulation transistor connected in common to the emitters of said input and reference transistors for regulating the emitter currents; a resistor connected to the emitter of said regulation transistor; a biasing means having a series connection of a junction diode and a Schottky diode connected in parallel between the base of said regulation transistor and said resistor; and an output terminal being coupled to at least one collector of said input and reference transistors.
Claim 10
Dependent Claim
69 words
A current mode logic circuit as set forth in claim 5, wherein said biasing means include a biasing transistor, the collector thereof being connected to the base of said reference transistor for providing the reference voltage and a resistor connected to the emitter of said biasing transistor, the base of said biasing transistor and said resistor constituting a series circuit which circuit is in parallel with said series connection.
Claim 11
Dependent Claim
203 words
A current mode logic circuit comprising; an input transistor being supplied with input signals through the base thereof; a reference transistor being given with a reference voltage through the base thereof; the emitter thereof being connected to the emitter of said input transistor; a regulation transistor connected in common through the collector thereof to the emitters of said input and reference transistors for regulating the emitter currents; load resistors coupled respectively to the collectors of said input and reference transistors for generating an output signal; a first resistor being coupled to the emitter of said regulation transistor; a biasing circuit having a series connection of a junction diode and a Schottky diode which are coupled in parallel between said first resistor and the base of said regulation transistor, and a biasing transistor, the collector thereof being coupled to the base of said reference transistor for giving the reference voltage, the emitter thereof being coupled to a second resistor, the base thereof and said second resistor being coupled in parallel to said series connection; and a power supply source having a first power terminal connected to said load resistors respectively and a second power terminal connected the first resistor for providing a power potential.
Claim 12
Dependent Claim
203 words
A current mode logic circuit comprising; an input transistor being supplied with input signals through the base thereof; a reference transistor being given with a reference voltage through the base thereof; the emitter thereof being connected to the emitter of said input transistor; a regulation transistor connected in common through the collector thereof to the emitters of said input and reference transistors for regulating the emitter currents; load resistors coupled respectively to the collectors of said input and reference transistors for generating an output signal; a first resistor being coupled to the emitter of said regulation transistor; a biasing circuit having a series connection of a junction diode and a Schottky diode which are coupled in parallel between said first resistor and the base of said regulation transistor, and a biasing transistor, the collector thereof being coupled to the base of said reference transistor for giving the reference voltage, the emitter thereof being coupled to a second resistor, the base thereof and said second resistor being coupled in parallel to said series connection; and a power supply source having a first power terminal connected to said load resistors respectively and a second power terminal connected the first resistor for providing a power potential.
Claim 13
Dependent Claim
58 words
A current mode logic circuit as set forth in claim 7, wherein said biasing circuit includes first and second biasing resistors, the first biasing resistor being coupled between the base of said biasing transistor and said load resistors respectively, and the second biasing resistor being coupled between the collector of said biasing transistor and said load resistors respectively.
Claim 14
Dependent Claim
24 words
A current logic circuit as set forth in claim 7 or claim 8, wherein said first power terminal is connected to the ground potential.
Claim 15
Dependent Claim
128 words
In a logic circuit, with power supply, including emitter-coupled transistors, the base of one of which being supplied with an input signal, the base of the other being served with a voltage; a regulation transistor for regulating the emitter current of said coupled transistors, a biasing means having a series connection including at least a junction diode, said biasing means generating a predetermined voltage between the emitter and the base of said regulation transistor; and an output terminal being coupled to at least one collector of the transistors the improvement comprising means for rendering the logic circuit substantially stabilized against variations in power supply voltage by stabilizing said voltage served to the base of the said other transistor, comprising in series with said junction diode, a Schottky diode.
Claim 16
Dependent Claim
128 words
In a logic circuit, with power supply, including emitter-coupled transistors, the base of one of which being supplied with an input signal, the base of the other being served with a voltage; a regulation transistor for regulating the emitter current of said coupled transistors, a biasing means having a series connection including at least a junction diode, said biasing means generating a predetermined voltage between the emitter and the base of said regulation transistor; and an output terminal being coupled to at least one collector of the transistors the improvement comprising means for rendering the logic circuit substantially stabilized against variations in power supply voltage by stabilizing said voltage served to the base of the said other transistor, comprising in series with said junction diode, a Schottky diode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-02-03 | 1984-08-04 | 1985-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-02-03 | 1988-08-04 | 1989-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-02-03 | 1992-08-04 | 1993-02-03 | $7700.00 | Window Closed / Lapsed |