Patent US1434201A successfully refreshed from Google Patents.
Patent US4247932A successfully refreshed from Google Patents.
US4247932A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic timepiece
Assignee: NEC Corp
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Filing: 1979-08-27
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Granted: 1981-01-27
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Expires: 1999-08-27
Abstract
Abstract An electronic timepiece includes frequency-dividing circuit means for generating a first signal of at least 1 Hz from a signal of a predetermined frequency. This first signal is counted by a time counter. The frequency-dividing circuit and the time counter are reset in response to the closing of a first input switch. Circuitry is provided for releasing the frequency-dividing circuit from its reset condition to generate a second signal of at least 1 Hz as a quick advance signal for time setting in response to the closing of a second input switch.
Inventors
- 👤 Yukuo Kodama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 11:00
CPC Classifications
G; G04; G04G; G04G5/00; G04G5/02
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
213 words
A quick advancing signal generator for adjusting an electronic timepiece comprising frequency dividing means for generating a first signal of at least 1 Hz from a signal of a predetermined frequency, a "second" counter for counting said 1 Hz signal and including a reset terminal, an output terminal, a first input switch having a first and a second state, a second input switch having a first and a second state, means for generating a reset signal during the first state of said first input switch, means for applying said reset signal to the reset terminal of said "second" counter, first gating means for transferring said first signal from said frequency dividing means to said output terminal as a quick advancing signal in response to the first state of said second input switch, and second gating means for transferring said reset signal to said frequency dividing means in response to the second state of said second input switch to reset said frequency dividing means, said first gating means comprising, an OR gate having two inputs, said inputs being supplied with said first signal and a signal representing one of said first and second states of said second input switch, respectively, and an output of said first gating means being applied to said output terminal.
Claim 2
Dependent Claim
213 words
A quick advancing signal generator for adjusting an electronic timepiece comprising frequency dividing means for generating a first signal of at least 1 Hz from a signal of a predetermined frequency, a "second" counter for counting said 1 Hz signal and including a reset terminal, an output terminal, a first input switch having a first and a second state, a second input switch having a first and a second state, means for generating a reset signal during the first state of said first input switch, means for applying said reset signal to the reset terminal of said "second" counter, first gating means for transferring said first signal from said frequency dividing means to said output terminal as a quick advancing signal in response to the first state of said second input switch, and second gating means for transferring said reset signal to said frequency dividing means in response to the second state of said second input switch to reset said frequency dividing means, said first gating means comprising, an OR gate having two inputs, said inputs being supplied with said first signal and a signal representing one of said first and second states of said second input switch, respectively, and an output of said first gating means being applied to said output terminal.
Claim 3
Dependent Claim
223 words
A quick advancing signal generator for adjusting an electronic timepiece comprising fequency dividing means for generating a first signal of at least 1 Hz from a signal of a predetermined frequency, a "second" counter for counting said 1 Hz signal and including a reset terminal, an output terminal for deriving a quick advancing signal a first input switch having a first and a second state, a second input switch having a first and a second state, means for generating a reset signal during the first state of said first input switch, means for applying said reset signal to the reset terminal of said "second" counter, first gating means for transferring said first signal from said frequency dividing means to said output terminal of the quick advancing signal in response to the first state of said second input switch and second gating means for transferring said reset signal to said frequency dividing means in response to the second state of said second input switch to reset said frequency dividing means, said second gating means comprising an AND gate having two inputs, said two inputs being supplied with said reset signal and a signal representing said first and second states of said second input switch, respectively, and an output of said second gating means being applied to the reset terminal of said frequency dividing means.
Claim 4
Dependent Claim
223 words
A quick advancing signal generator for adjusting an electronic timepiece comprising fequency dividing means for generating a first signal of at least 1 Hz from a signal of a predetermined frequency, a "second" counter for counting said 1 Hz signal and including a reset terminal, an output terminal for deriving a quick advancing signal a first input switch having a first and a second state, a second input switch having a first and a second state, means for generating a reset signal during the first state of said first input switch, means for applying said reset signal to the reset terminal of said "second" counter, first gating means for transferring said first signal from said frequency dividing means to said output terminal of the quick advancing signal in response to the first state of said second input switch and second gating means for transferring said reset signal to said frequency dividing means in response to the second state of said second input switch to reset said frequency dividing means, said second gating means comprising an AND gate having two inputs, said two inputs being supplied with said reset signal and a signal representing said first and second states of said second input switch, respectively, and an output of said second gating means being applied to the reset terminal of said frequency dividing means.
Claim 5
Independent Claim
251 words
A system for generating a quick advancing signal for time-setting in an electronic timepiece comprising frequency dividing means for generating a first signal of at least 1 Hz from a predetermined frequency, a "second" counter for counting said 1 Hz signal and including a reset terminal, an output terminal, a first input switch having a first and a second state, a second input switch having a first and a second state, means for generating a reset signal during the first state of said first input switch, means for applying said reset signal to the reset terminal of said "second" counter, first gating means having two inputs, one of said two inputs being supplied with a signal representing said first and second state of said second input switch, the other of said two inputs being supplied with said first signal, said first gating means being controlled by the signal representing said first state of said second input switch to transfer said first signal to said output terminal as said quick advancing signal, second gating means having two inputs, one of said two inputs of said second gating means being supplied with the signal representing said first and second state of said second input switch, the other of said two inputs of said second gating means being supplied with said reset signal, said second gating means being controlled by the signal representing said second state of said second input switch to transfer said reset signal to the reset terminal of said dividing means.
Claim 6
Independent Claim
251 words
A system for generating a quick advancing signal for time-setting in an electronic timepiece comprising frequency dividing means for generating a first signal of at least 1 Hz from a predetermined frequency, a "second" counter for counting said 1 Hz signal and including a reset terminal, an output terminal, a first input switch having a first and a second state, a second input switch having a first and a second state, means for generating a reset signal during the first state of said first input switch, means for applying said reset signal to the reset terminal of said "second" counter, first gating means having two inputs, one of said two inputs being supplied with a signal representing said first and second state of said second input switch, the other of said two inputs being supplied with said first signal, said first gating means being controlled by the signal representing said first state of said second input switch to transfer said first signal to said output terminal as said quick advancing signal, second gating means having two inputs, one of said two inputs of said second gating means being supplied with the signal representing said first and second state of said second input switch, the other of said two inputs of said second gating means being supplied with said reset signal, said second gating means being controlled by the signal representing said second state of said second input switch to transfer said reset signal to the reset terminal of said dividing means.
Claim 7
Dependent Claim
15 words
The system of claim 3, further comprising means for generating said signal of predetermined frequency.
Claim 8
Dependent Claim
17 words
The system of claim 3, further comprising a quartz oscillator for generating said signals of predetermined frequency.
Claim 9
Dependent Claim
204 words
Time-setting apparatus for time-setting in an electronic timepiece comprising frequency dividing means for generating a first signal of at least 1 Hz from a signal of a predetermined frequency and including a reset terminal, a "second" counter for counting said first signal and including a reset terminal, a first input switch for generating an output, said output having a first and a second level, a second input switch for generating an output, said output having a third and a fourth level, means for generating a reset signal in response to receiving said first level, means for applying said reset signal to the reset terminal of said "second" counter, a first gate for receiving said first signal and the output of said second input switch, and a second gate for receiving said reset signal and the output of said second input switch, said first gate transferring said first signal to a minute counter in an electronic timepiece as a quick advancing signal when siad output of said second input switch is in said third level, and said second gate transferring said reset signal to the reset terminal of said frequency dividing means when said output of said second input switch is in said fourth level.
Claim 10
Dependent Claim
204 words
Time-setting apparatus for time-setting in an electronic timepiece comprising frequency dividing means for generating a first signal of at least 1 Hz from a signal of a predetermined frequency and including a reset terminal, a "second" counter for counting said first signal and including a reset terminal, a first input switch for generating an output, said output having a first and a second level, a second input switch for generating an output, said output having a third and a fourth level, means for generating a reset signal in response to receiving said first level, means for applying said reset signal to the reset terminal of said "second" counter, a first gate for receiving said first signal and the output of said second input switch, and a second gate for receiving said reset signal and the output of said second input switch, said first gate transferring said first signal to a minute counter in an electronic timepiece as a quick advancing signal when siad output of said second input switch is in said third level, and said second gate transferring said reset signal to the reset terminal of said frequency dividing means when said output of said second input switch is in said fourth level.
Claim 11
Dependent Claim
41 words
The generator according to claim 1 or 2, in which said first input switch includes a first single pole switch and a flip-flop whose state is reversed in response to a change in the state of said first single pole switch.
Claim 12
Dependent Claim
19 words
The generator according to claim 1 or 2, in which said first and second input switches include inverter circuits.
Claim 13
Dependent Claim
18 words
The system according to claim 3, in which said first input switch includes a first single pole switch.
Claim 14
Dependent Claim
26 words
The system according to claim 9, in which said second input switch includes a second single pole switch operable independently of said first single pole switch.
Claim 15
Dependent Claim
16 words
The system according to claim 9, in which said first gating means includes an OR gate.
Claim 16
Dependent Claim
16 words
The system according to claim 9, in which said second gating means includes an AND gate.
Claim 17
Dependent Claim
21 words
The system according to claim 3, in which said means for generating includes a flip-flop controlled by said first input switch.
Claim 18
Dependent Claim
37 words
The apparatus according to claim 6, in which said first input switch includes a first single pole switch and said second input switch includes a second single pole switch operable independently of said first single pole switch.
Claim 19
Dependent Claim
15 words
The apparatus according to claim 6, in which said first gate includes an OR gate.
Claim 20
Dependent Claim
21 words
The apparatus according to claim 6, in which said means for generating includes a flip-flop circuit controlled by said first signal.
References Cited (Backward Citations)
US3871168A
Cited
US4022017A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-27 | 1984-07-28 | 1985-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-27 | 1988-07-28 | 1989-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-27 | 1992-07-28 | 1993-01-27 | $7700.00 | Window Closed / Lapsed |