Patent US4247920A successfully refreshed from Google Patents.
US4247920A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory access system
Assignee: Tektronix Inc
•
Filing: 1979-04-24
•
Granted: 1981-01-27
•
Expires: 1999-04-24
Abstract
Abstract A means and method for accessing a digital memory system in a manner permitting the transfer of a two-byte information signal into and out of a storage area defined by any two logically adjacent memory bytes. Provision is also made for maintaining a preselected locational integrity between the bytes forming the information signal.
Inventors
- 👤 Richard A. Springer
- 👤 John G. Theus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:05
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/04
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
234 words
A memory access system comprising: (a) first and second memory modules each having M locations for storing a byte of digital information, with each said storage location being accessible via a different system address signal, said memory modules defining in concept a single memory space of 2M storage locations ordered such that each said location in each said module represents a next sequential location for a different said location in the other said module; (b) means for receiving a system address signal defining a storage location to be accessed; (c) means for receiving a control signal defining a memory operation to be performed; (d) means responsive to said control signal and said system address signal for simultaneously accessing a first storage location defined by said address signal in one of said memory modules and a next sequential storage location in the other of said memory modules irrespective of which of said first and second memory modules contains said first storage location; and (e) means also responsive to said control signal and said system address signal for simultaneously transferring a first byte of digital information into or out of said first storage location and a second byte of digital information into or out of said next sequential storage location while maintaining a predetermined logical interrelationship between said first and second digital bytes, also irrespective of which of said memory modules contains said first storage location.
Claim 2
Dependent Claim
234 words
A memory access system comprising: (a) first and second memory modules each having M locations for storing a byte of digital information, with each said storage location being accessible via a different system address signal, said memory modules defining in concept a single memory space of 2M storage locations ordered such that each said location in each said module represents a next sequential location for a different said location in the other said module; (b) means for receiving a system address signal defining a storage location to be accessed; (c) means for receiving a control signal defining a memory operation to be performed; (d) means responsive to said control signal and said system address signal for simultaneously accessing a first storage location defined by said address signal in one of said memory modules and a next sequential storage location in the other of said memory modules irrespective of which of said first and second memory modules contains said first storage location; and (e) means also responsive to said control signal and said system address signal for simultaneously transferring a first byte of digital information into or out of said first storage location and a second byte of digital information into or out of said next sequential storage location while maintaining a predetermined logical interrelationship between said first and second digital bytes, also irrespective of which of said memory modules contains said first storage location.
Claim 3
Dependent Claim
59 words
The memory access system of claim 1 wherein the storage locations of said first and second memory modules are defined as odd and even, respectively, and wherein said means (d) includes means responsive to a system address signal of even value N for accessing a storage location in each said memory module at a module address defined by N/2.
Claim 4
Dependent Claim
67 words
The memory access system of claim 2 wherein said means (d) further includes means responsive to a system address signal of odd value N for accessing a first storage location in said first memory module at a module address defined by the integer part of N/2 and at a second storage location in said second memory module at module address defined by the integer part of (N+1)/2.
Claim 5
Dependent Claim
84 words
The memory access system of claim 1 wherein said means (e) includes means for simultaneously transferring said first and second bytes of digital information into or out of said first and next sequential storage locations, respectively, as a two-byte word of digital information, with the upper byte of said word being defined by said first byte and the lower byte of said word being defined by said second byte irrespective of which of said first and second memory modules contains said first storage location.
Claim 6
Dependent Claim
52 words
The memory access system of claim 4 wherein each said byte of digital information is n digital bits long and wherein the n bits of said first byte form the high-order n bits of said word and the n bits of said second byte form the low-order n bits of said byte.
Claim 7
Independent Claim
248 words
A method of accessing a digital memory system comprising the steps of: (a) providing first and second memory modules each having M locations for storing a byte of digital information, with each said storage location in each said module being accessible via a different system address signal, said memory modules defining in concept a single memory space of 2M storage locations ordered such that each said location in each said module represents a next sequential location for a different said location in the other said module; (b) receiving a system address signal defining a storage location to be accessed; (c) receiving a control signal defining a memory operation to be performed; (d) responsive to the receipt of a said control signal and a said system address signal, simultaneously accessing a first storage location defined by said address signal in one of said memory modules and a next sequential storage location in the other of said memory modules irrespective of which of said first and second memory modules contains said first storage location; and (e) also responsive to the receipt of a said control signal and a said system address signal, simultaneously transferring a first byte of digital information into or out of said first storage location and a second byte of digital information into or out of said next sequential storage location while maintaining a predetermined logical interrelationship between said first and second digital bytes, also irrespective of which of said memory modules contains said first storage location.
Claim 8
Independent Claim
248 words
A method of accessing a digital memory system comprising the steps of: (a) providing first and second memory modules each having M locations for storing a byte of digital information, with each said storage location in each said module being accessible via a different system address signal, said memory modules defining in concept a single memory space of 2M storage locations ordered such that each said location in each said module represents a next sequential location for a different said location in the other said module; (b) receiving a system address signal defining a storage location to be accessed; (c) receiving a control signal defining a memory operation to be performed; (d) responsive to the receipt of a said control signal and a said system address signal, simultaneously accessing a first storage location defined by said address signal in one of said memory modules and a next sequential storage location in the other of said memory modules irrespective of which of said first and second memory modules contains said first storage location; and (e) also responsive to the receipt of a said control signal and a said system address signal, simultaneously transferring a first byte of digital information into or out of said first storage location and a second byte of digital information into or out of said next sequential storage location while maintaining a predetermined logical interrelationship between said first and second digital bytes, also irrespective of which of said memory modules contains said first storage location.
Claim 9
Dependent Claim
92 words
The memory access method of claim 6 wherein said step (d) includes, responsive to a system address signal of even value N, accessing a storage location in each said memory module at a module address defined by N/2 and, responsive to a system address signal of odd value N, accessing a first storage location in said first memory module at a module address defined by the interger part of N/2 and at a second storage location in said second memory module at a module address defined by the interger part of (N+1)/2.
Claim 10
Dependent Claim
76 words
The memory access method of claim 6 wherein said step (e) includes transferring said first and second bytes of digital information into or out of said storage locations as a two-byte word of digital information, with the upper byte of said word being defined by said first byte and the lower byte of said word being defined by said second byte irrespective of which of said first and second memory modules contains said first storage location.
References Cited (Backward Citations)
GB1254929A
Cited
US3771145A
Cited
US3771145B1
Cited
US3828320A
Cited
US3846765A
Cited
US3858187A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-27 | 1984-07-28 | 1985-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-27 | 1988-07-28 | 1989-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-27 | 1992-07-28 | 1993-01-27 | $7700.00 | Window Closed / Lapsed |