Punch-through load devices in high density static memory cell

Claim 1

A static memory cell of the type formed in a face of a semiconductor body and having: a pair of driver transistors each having source and drain regions, a channel, and a gate, the source and drain regions being formed by heavily doped regions in the face of the semiconductor body, the gates overlying the channels and separated therefrom by a gate oxide layer; conductive means separately connecting the drain regions of each of the driver transistors to the gate of the other driver transistor to provide a cross-coupled bistable circuit, the conductive means overlying said layer of field oxide; a pair of access transistors each having a source to drain path and a gate; p1 a pair of data lines on said face with means coupling each date line separately through the source to drain path of a different one of the access transistors to the drain region of a different one of the driver transistors; and an address line on said face connected to the gate of both of the access transistors; the improvement comprising: a pair of load devices at said face of the body with each load device being a punch-through MOS short channel transistor having one electrode coupled to a voltage supply line on said face and a second electrode coupled separately to a different one of said drain regions on the driver transistors.