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US4247343A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making semiconductor integrated circuits

Assignee: Individual
•
Filing: 1978-10-25
•
Granted: 1981-01-27
•
Expires: 1998-10-25
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Abstract

Abstract The proposed method of making semiconductor integrated circuits comprises sequential formation on a p-substrate of a first layer of n-regions, an epitaxial p-layer, a second layer of n-regions with an oxide layer, a third layer of p- and n-regions formed by opening holes in the oxides layer and ionic implantation of appropriate dopants, as well as deep diffusion of the latter, conducted in an inert medium, the final step being interconnection metallization. A semiconductor integrated circuit thus produced comprises p-resistors based on a portion of the epitaxial p-layer, confined by n-regions, n-p-n transistors each having a collector isolating it from the other circuit components and based on n-regions of the first and second layers, a base formed by a portion of the epitaxial p-layer and confined by the collector region, and an emitter in the form of an n-region of the third layer, made in the base region. The circuit also comprises p-n-p transistors in a common-collector arrangement, n-resistors and lateral p-n-p transistors based on n-regions of the second layer and shaped as a prism the entire base whereof is contiguous to the substrate and the surface portion whereof contains at least one p-region of the third layer and/or at least one n-region of the third layer, the hole concentration in the p-regions of the third layer being at least five times higher than the electron concentration in the n-regions of the second layer.

Inventors

  • 👤 Jury V. Kruzhanov
  • 👤 Viktor P. Dubinin
  • 👤 Viktor I. Ovchinnikov
  • 👤 Vladimir E. Safronov

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 18:04
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/21; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10D84/611; H10P30/202; H10P30/204; H10P30/28

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 171 words
A method of making semiconductor integrated circuits, comprising forming in the surface layer of a p conductivity type semiconductor substrate a first layer including a plurality of n conductivity type layers; depositing on the surface of said substrate an epitaxial layer of p conductivity type; forming in said epitaxial layer a second layer including a plurality of regions of n conductivity type, with an oxide layer being formed on the surface; forming in the surface layer a third layer including a plurality of p conductivity type and n conductivity type regions, including the steps of opening holes in said oxide layer to form regions of a first conductivity type, implanting a dopant of a first type, opening holes in the same oxide layer to form regions of a second conductivity type, implanting a dopant of a second type in a concentration insufficient for inverting the conductivity type in said regions of the first conductivity type, and depth diffusing said dopants of both types in an inert medium; and applying metal conductors.
Claim 2
Independent Claim 171 words
A method of making semiconductor integrated circuits, comprising forming in the surface layer of a p conductivity type semiconductor substrate a first layer including a plurality of n conductivity type layers; depositing on the surface of said substrate an epitaxial layer of p conductivity type; forming in said epitaxial layer a second layer including a plurality of regions of n conductivity type, with an oxide layer being formed on the surface; forming in the surface layer a third layer including a plurality of p conductivity type and n conductivity type regions, including the steps of opening holes in said oxide layer to form regions of a first conductivity type, implanting a dopant of a first type, opening holes in the same oxide layer to form regions of a second conductivity type, implanting a dopant of a second type in a concentration insufficient for inverting the conductivity type in said regions of the first conductivity type, and depth diffusing said dopants of both types in an inert medium; and applying metal conductors.
Claim 3
Dependent Claim 31 words
A method as claimed in claim 1, wherein said ionic implantation of said dopant of said first type is followed by additional deep diffusion of said dopant in an inert medium.

References Cited (Backward Citations)

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US3575741A Cited
US3717507A Cited
US4054899A Cited
US3969748A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1984-01-27 1984-07-28 1985-01-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1988-01-27 1988-07-28 1989-01-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1992-01-27 1992-07-28 1993-01-27 $7700.00 Window Closed / Lapsed

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