US4246642A — Leaky digital integrator

Claim 1

Independent Claim 181 words

An adaptive leaky integrator circuit comprising: accumulator means including an adder having first and second adder input terminals and an adder output terminal, and a shift register coupling the adder output terminal back to the second adder input terminal and to an integrator output terminal; ternary operator means coupled to said integrator output terminal and operative to develop one of three decay factor signals depending upon whether the integrator output signal level is above, equal to, or below a predetermined reference level; and switching means having a first switched terminal which is periodically coupled at a first rate to the first adder input terminal to input update data signals to the accumulator circuit, and a second switched terminal which is periodically coupled at a second rate to the first adder input terminal to input decay data signals to the accumulator circuit such that the circuit as a whole performs according to the equation a.sub.i (t)=Da.sub.i (t-1)+Δa.sub.i (t) where a i (t) is the integrator output at time t, D is the decay factor and Δa i (t) is the update increment.

Claim 2

Dependent Claim 181 words

An adaptive leaky integrator circuit comprising: accumulator means including an adder having first and second adder input terminals and an adder output terminal, and a shift register coupling the adder output terminal back to the second adder input terminal and to an integrator output terminal; ternary operator means coupled to said integrator output terminal and operative to develop one of three decay factor signals depending upon whether the integrator output signal level is above, equal to, or below a predetermined reference level; and switching means having a first switched terminal which is periodically coupled at a first rate to the first adder input terminal to input update data signals to the accumulator circuit, and a second switched terminal which is periodically coupled at a second rate to the first adder input terminal to input decay data signals to the accumulator circuit such that the circuit as a whole performs according to the equation a.sub.i (t)=Da.sub.i (t-1)+Δa.sub.i (t) where a i (t) is the integrator output at time t, D is the decay factor and Δa i (t) is the update increment.

Claim 3

Dependent Claim 76 words

An adaptive integrator circuit as recited in claim 1 wherein said ternary operator means causes said decay signal to have a negative predetermined value if said integrator output signal is above said reference level, causes said decay signal to be of zero value if said integrator output signal is substantially equal to said reference level, and causes said decay signal to have a positive predetermined value if said integrator output signal is below said reference level.

Claim 4

Dependent Claim 99 words

An adaptive leaky integrator circuit as recited in claim 1 wherein said ternary operator means includes means for determining the difference between said integrator output signal and said predetermined reference level and for developing a difference signal commensurate therewith, means for determining whether said difference signal is positive or negative and for developing a sign signal commensurate therewith, means for determining whether said difference signal is equal to zero or is different from zero and for developing a data signal commensurate therewith, and multiplier means for multiplying said data signal by said sign signal to develop said decay signal.

Claim 5

Dependent Claim 79 words

An adaptive leaky integrator circuit as recited in claim 1 wherein said switching means includes a first switching element which alternately couples said first adder input terminal to said first switched terminal and a second switched terminal, and a second switching element which normally couples said first adder input terminal to a third switched terminal for receiving a zero value signal but periodically couples said first adder input terminal to a fourth switched terminal for receiving said decay signal.

Claim 6

Dependent Claim 31 words

An adaptive leaky integrator circuit as recited in claim 4 wherein said second switching element couples said fourth switched terminal to said first adder input terminal through said second switched terminal.

Claim 7

Dependent Claim 178 words

An adaptive leaky integrator circuit comprising: adder means having first and second input terminals and operative to add digital signals input thereto to develop a summation signal; switching means having third and fourth input terminals and operative to periodically couple each of said third and fourth input terminals to said first input terminal; output terminal means; signal delay means for delaying said summation signal and for coupling the delayed summation signal to said second input terminal and to said output terminal means; and signal monitoring means for monitoring the signal level at said output terminal means and for determining whether or not the level of said delayed summation signal is above or below a predetermined reference level, for developing a decay signal commensurate therewith and for coupling said decay signal to said fourth input terminal so that it may be input by said switching means to said adder means wherein said delayed summation signal approximates the integral of update signals applied to said third input terminal modified by a slight decay factor as determined by said decay signal.

Claim 8

Dependent Claim 178 words

An adaptive leaky integrator circuit comprising: adder means having first and second input terminals and operative to add digital signals input thereto to develop a summation signal; switching means having third and fourth input terminals and operative to periodically couple each of said third and fourth input terminals to said first input terminal; output terminal means; signal delay means for delaying said summation signal and for coupling the delayed summation signal to said second input terminal and to said output terminal means; and signal monitoring means for monitoring the signal level at said output terminal means and for determining whether or not the level of said delayed summation signal is above or below a predetermined reference level, for developing a decay signal commensurate therewith and for coupling said decay signal to said fourth input terminal so that it may be input by said switching means to said adder means wherein said delayed summation signal approximates the integral of update signals applied to said third input terminal modified by a slight decay factor as determined by said decay signal.

Claim 9

Dependent Claim 83 words

An adaptive leaky integrator circuit as recited in claim 6 wherein said signal monitoring means is a ternary operator circuit which causes said decay signal to have a negative predetermined value if said delayed summation signal is above said reference level, causes said decay signal to be of zero value if said delayed summation signal is substantially equal to said reference level, and causes said decay signal to have a positive predetermined value if said delayed summation signal is beneath said reference level.

Claim 10

Dependent Claim 71 words

An adaptive leaky integrator circuit as recited in claim 6 wherein said switching means includes a first switching element which alternately couples said first input terminal to said third input terminal and a fifth input terminal, and a second switching element which normally couples said fifth input terminal to a sixth input terminal for receiving a zero value signal but periodically couples said fifth input terminal to said fourth input terminal.

Claim 11

Dependent Claim 39 words

An adaptive leaky integrator circuit as recited in claim 8 wherein said switching means further includes means for controlling the switching period of said second switching element such that it controls the effective time constant of the integrator circuit.

Claim 12

Dependent Claim 100 words

An adaptive leaky integrator circuit as recited in claim 6 wherein said signal monitoring means includes means for determining the difference between said delayed summation signal and said predetermined reference level and for developing a difference signal commensurate therewith, means for determining whether said difference signal is positive or negative and for developing a sign signal commensurate therewith, means for determining whether said difference signal is equal to zero or is different from zero and for developing a difference determining signal commensurate therewith, and multiplier means for multiplying said determining signal by said sign signal to develop said decay signal.

Claim 13

Dependent Claim 147 words

In an equalizer means having a plurality of taps, means for correlating the taps with an input signal and for developing tap update signals commensurate therewith, and leaky integrator means for integrating each of said update signals and for developing tap coefficient signals for modifying the output of the equalizer, an improved leaky integrator circuit comprising: accumulator means for accumulating update signals and for developing a tap coefficient signal; means for alternately and periodically coupling said update signals into said accumulator means and for similarly coupling one of a plurality of predetermined decay signals into said accumulator means so as to cause said tap coefficient to decay toward a predetermined reference value; and means for monitoring said tap coefficient signal, for determining which of said plurality of predetermined decay signals is to be developed, and for developing the particular decay signal to be input to accumulator means.

Claim 14

Dependent Claim 147 words

In an equalizer means having a plurality of taps, means for correlating the taps with an input signal and for developing tap update signals commensurate therewith, and leaky integrator means for integrating each of said update signals and for developing tap coefficient signals for modifying the output of the equalizer, an improved leaky integrator circuit comprising: accumulator means for accumulating update signals and for developing a tap coefficient signal; means for alternately and periodically coupling said update signals into said accumulator means and for similarly coupling one of a plurality of predetermined decay signals into said accumulator means so as to cause said tap coefficient to decay toward a predetermined reference value; and means for monitoring said tap coefficient signal, for determining which of said plurality of predetermined decay signals is to be developed, and for developing the particular decay signal to be input to accumulator means.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1984-01-20	1984-07-21	1985-01-20	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1988-01-20	1988-07-21	1989-01-20	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1992-01-20	1992-07-21	1993-01-20	$7700.00	Window Closed / Lapsed

Leaky digital integrator

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