Automatic adaptive equalizer implementation amenable to mos

Claim 2

An automatic equalizer comprising a first recirculating shift register for receiving a sampled digital data transmission signal; a first multiplier means for serially receiving the output of said first shift register; an accumulator for receiving the product signal from said first multiplier and the output signal fed back from said accumulator; means for providing a signal proportional to the major sample of the impulse response of the overall transmission system; means for providing a signal proportional to the estimated value of a received digit; means for forming the product of said provided two signals and for providing an output signal proportional to said product; comparator means for receiving the said provided product signal and the output signal of said accumulator to form a sign difference signal; a second recirculating register for storing digits corresponding to gain settings; incrementing means receiving the sign difference signal from said comparator means and the sign signal indicative of the sign of the signal entering said first recirculating shift register for providing an incrementing signal to said second recirculating shift register so as to increment the digits corresponding to gain settings in a direction proportional to the sign of the product of said sign difference signal and the sign of the signal from said first recirculating shift register; and an output register for serially receiving the output signal of said second recirculating register and for providing said serially received signal in parallel output to said first multiplier means for multiplication with the output from said first recirculatory shift register.

Claim 3

The automatic equalizer according to claim 1 and further comprising: means for providing a signal indicative of a fixed gain factor; switch means interposed between the output of said first multiplier and the input to said accumulator for disconnecting the output of said first multiplier from said accumulator input and for connecting the output of said first recirculating shift register to said accumulator input at a time corresponding to the position of said fixed gain factor with respect to the serial output of said first shift register.

Claim 4

The invention according to claim 2 wherein said incrementing means is comprised of: an exclusive OR gate for receiving at its inputs the sign difference signal and the sign signal indicative of the sign of the signal entering said first recirculating shift register; a summation device for receiving as one input the output from said second recirculating register and as another input the input from said exclusive OR gate.

Claim 5

The invention according to claim 3 and further comprising: counter means connected to the output of said exclusive OR gate; switch means interposed between the output of said exclusive OR gate and one input of said summation means for connecting the output of said exclusive OR gate to the input of said summation means or connecting the output of said counter means to the input of said summation means.

Claim 6

The invention according to claim 3 and further comprising: a switch means interposed between the input to said first recirculating shift register and one input of said exclusive OR gate for connecting said one exclusive OR gate input to said shift register input upon the arrival of a recirculated sample at the input of said first recirculating shift register.

Claim 7

An automatic equalizer comprising a first recirculating shift register for receiving a sampled digital data transmission signal; a first multiplier means for serially receiving the output of said first shift register; an accumulator for receiving the product signal from said first multiplier and the output signaL fed back from said accumulator; a decision means for receiving as an input the output of said accumulator means, said decision means determining the approximate digital level of the signal from said accumulator means as compared against an estimated value of a major sample of the system''s input response and, in addition, providing a sign signal of said approximate digital level; a second multiplier means for multiplying the estimated signal level from said decision means with the estimated value of the major sample of the system''s impulse response; a digital comparator for comparing the multiplied signal from said second multiplier means with the output signal from said accumulator to form a sign difference signal; an exclusive OR gate receiving as inputs the sign signal from said decision means and the sign difference signal from said digital comparator; an accumulator connected to receive the output from said exclusive OR gate for accumulating the output from said exclusive OR gate to provide said estimated value of the major sample of the system''s impulse response. a second recirculating register for storing digits corresponding to gain settings; incrementing means receiving the sign difference signal from said comparator means and the sign signal indicative of the sign of the signal entering said first recirculating shift register for providing an incrementing signal to said second recirculating shift register so as to increment the digits corresponding to gain settings in a direction corresponding to the sign of the product of said sign difference signal and the sign of the signal from said first recirculating shift register; and an output register for serially receiving the output signal of said second recirculating register and for providing said serially received signal in parallel output to said first multiplier means for multiplication with the output from said first recirculatory shift register.

Claim 8

An automatic equalizer comprising a first recirculating shift register for receiving a sampled digital data transmission signal; a first multiplier means for serially receiving the output of said first shift register; an accumulator for receiving the product signal from said first multiplier and the output signaL fed back from said accumulator; a decision means for receiving as an input the output of said accumulator means, said decision means determining the approximate digital level of the signal from said accumulator means as compared against an estimated value of a major sample of the system''s input response and, in addition, providing a sign signal of said approximate digital level; a second multiplier means for multiplying the estimated signal level from said decision means with the estimated value of the major sample of the system''s impulse response; a digital comparator for comparing the multiplied signal from said second multiplier means with the output signal from said accumulator to form a sign difference signal; an exclusive OR gate receiving as inputs the sign signal from said decision means and the sign difference signal from said digital comparator; an accumulator connected to receive the output from said exclusive OR gate for accumulating the output from said exclusive OR gate to provide said estimated value of the major sample of the system''s impulse response. a second recirculating register for storing digits corresponding to gain settings; incrementing means receiving the sign difference signal from said comparator means and the sign signal indicative of the sign of the signal entering said first recirculating shift register for providing an incrementing signal to said second recirculating shift register so as to increment the digits corresponding to gain settings in a direction corresponding to the sign of the product of said sign difference signal and the sign of the signal from said first recirculating shift register; and an output register for serially receiving the output signal of said second recirculating register and for providing said serially received signal in parallel output to said first multiplier means for multiplication with the output from said first recirculatory shift register.

Claim 9

The automatic equalizer according to claim 6 and further comprising: means for providing a signal indicative of a fixed gain factor; switch means interposed between the output of said first multiplier and the input to said accumulator for disconnecting the output of said multiplier from said accumulator input and for connecting said means for providing said fixed gain factor to the accumulator input at a time corresponding to the proper position of said fixed gain factor with respect to the serial output of said first shift register.

Claim 10

The invention according to claim 6 wherein said incrementing means is comprised of: a second exclusive OR gate for receiving at its inputs the sign difference signal and the sign signal indicative of the sign of the signal entering said first recirculating shift register; a summation device for receiving as one input the output from said second recirculating register and as another input the output from said second exclusive OR gate.

Claim 11

The invention according to claim 8 and further comprising: counter means connected to the output of said second exclusive OR gate; and switch means interposed between the output of said second exclusive OR gate and one input of said summation device for connecting the output of said second exclusive OR gate to the input of said second recirculating shift register or connecting the output of said counter means to the input of said second recirculating shift register.

Claim 12

The invention according to claim 8 and further comprising: a switch means interposed between the input to said first recirculating shift register and one input of said second exclusive OR gate for connecting said one second exclusive OR gate input to said shift register input upon the arrival of a recirculated sample at the input of said first recirculating shift register.

Claim 13

An automatic adaptive equalizer comprising: means for sampling a received signal to provide a signal xi, which is a digitized sample oF the received signal taken once each baud time; a m+n+1 stage register means for receiving said xi signal such that during the ith baud interval signal sample xi n feeds into the register and the signal samples xi m through xi n feed serially out of the x-register and all samples except xi m recirculate back to the input of said register means; multiplier means connected to receive the serial output from said register means; a second storage means for storing and recirculating gain factors, g, once each baud time in synchronization with the circulation of x''s in the said first named register means; a summation means receiving the recirculating gain factors and summing therewith an incremental signal Delta g + or - 1 and for feeding the sum signal to the input of said second storage means; a g-output register for serially receiving the gain factors, g, from said second storage means and for providing said gain factors in parallel to said multiplier means for multiplication with the serial output from said register means; means for accumulating the output from said multiplier means to form the equalizer output yi where: means for providing an estimated signal yiD of the value of the signal yi with intersymbol interference removed; comparator means providing a signal Sgn Vi which is the sign signal of the quantity Yi where Yi is an estimate of the error in the equalizer output and is defined by equations Yi yi -yiD and; means for receiving the signal Sgn Yi and a signal Sgn xi k from the input of said m+n+1 stage register means for forming the product thereof the sign of which determines the direction in which Delta g is applied to said summation means.

Claim 14

An automatic adaptive equalizer comprising: means for sampling a received signal to provide a signal xi, which is a digitized sample oF the received signal taken once each baud time; a m+n+1 stage register means for receiving said xi signal such that during the ith baud interval signal sample xi n feeds into the register and the signal samples xi m through xi n feed serially out of the x-register and all samples except xi m recirculate back to the input of said register means; multiplier means connected to receive the serial output from said register means; a second storage means for storing and recirculating gain factors, g, once each baud time in synchronization with the circulation of x''s in the said first named register means; a summation means receiving the recirculating gain factors and summing therewith an incremental signal Delta g + or - 1 and for feeding the sum signal to the input of said second storage means; a g-output register for serially receiving the gain factors, g, from said second storage means and for providing said gain factors in parallel to said multiplier means for multiplication with the serial output from said register means; means for accumulating the output from said multiplier means to form the equalizer output yi where: means for providing an estimated signal yiD of the value of the signal yi with intersymbol interference removed; comparator means providing a signal Sgn Vi which is the sign signal of the quantity Yi where Yi is an estimate of the error in the equalizer output and is defined by equations Yi yi -yiD and; means for receiving the signal Sgn Yi and a signal Sgn xi k from the input of said m+n+1 stage register means for forming the product thereof the sign of which determines the direction in which Delta g is applied to said summation means.