Patent US4246500A successfully refreshed from Google Patents.
US4246500A
Expired / Lapsed
US
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Current mirror circuit
Assignee: Hitachi Ltd
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Filing: 1979-01-29
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Granted: 1981-01-20
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Expires: 1999-01-29
Abstract
Abstract A current mirror circuit wherein an I 2 L circuit is employed as the load of a current mirror circuit formed of a PNP (NPN) transistor, the injector of the I 2 L circuit is common with those of another group of I 2 L circuits, and a predetermined current is derived from the PNP (NPN) transistor of the current mirror circuit.
Inventors
- 👤 Yutaka Okada
- 👤 Tohru Nakamura
- 👤 Takahiro Okabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:40
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/091; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/265
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
203 words
A current mirror circuit comprising; a first transistor which has a plurality of collectors, in which the output of a first one of said collectors is fed back to the base of said first transistor, in which an output current is derived from a second one of said collectors, and the emitter of which is connected to a power supply; a second transistor which has a plurality of collectors, in which the output of a first one of said collectors is fed back to the base of said second transistor, in which a second one of said collectors is connected to the first collector of said first transistor, and the emitter of which is grounded; a third transistor the base of which is grounded, the collector of which is connected to the base of said second transistor, and the emitter of which serves as a current supplying terminal; and wherein said first collector output of said first transistor is fed back to the base thereof through a fourth transistor, the collector of which is grounded, the base of which is connected to said first collector of said first transistor, and the emitter of which is connected to the base of said first transistor.
Claim 2
Dependent Claim
203 words
A current mirror circuit comprising; a first transistor which has a plurality of collectors, in which the output of a first one of said collectors is fed back to the base of said first transistor, in which an output current is derived from a second one of said collectors, and the emitter of which is connected to a power supply; a second transistor which has a plurality of collectors, in which the output of a first one of said collectors is fed back to the base of said second transistor, in which a second one of said collectors is connected to the first collector of said first transistor, and the emitter of which is grounded; a third transistor the base of which is grounded, the collector of which is connected to the base of said second transistor, and the emitter of which serves as a current supplying terminal; and wherein said first collector output of said first transistor is fed back to the base thereof through a fourth transistor, the collector of which is grounded, the base of which is connected to said first collector of said first transistor, and the emitter of which is connected to the base of said first transistor.
Claim 3
Dependent Claim
77 words
A current mirror circuit according to claim 1, wherein said first and fourth transistors are PNP transistors, said second transistor is an NPN transistor, said third transistor is a lateral PNP transistor, said second and third transistors forming an I 2 L element, and the emitter of said third transistor serving as the injector of said I 2 L element being constructed in common with the injector of a logical circuit containing the I 2 L element.
Claim 4
Dependent Claim
34 words
A current mirror circuit according to claim 1, wherein the base of said second transistor is provided with a switching element which is connected to one of a ground terminal and an open terminal.
Claim 5
Dependent Claim
100 words
A current mirror circuit according to claim 1, wherein the area of the second collector of said second transistor is n times (wherein n is a positive integer or a fraction) as large as the area of the first collector thereof, and the area of the second collector of said first transistor is m times (wherein m is a positive integer or a fraction) as large as the area of the first collector thereof, whereby current to be derived from the second collector of said first transistor is n×m times as high as the base current of said second transistor.
Claim 6
Dependent Claim
69 words
A current mirror circuit according to claim 1, wherein said second transistor is an NPN transistor, said third transistor is a lateral PNP transistor, an I 2 L element is constructed of said second and third transistors, and the emitter of said third transistor to serve as an injector of said I 2 L element is constructed in common with the injector of an I 2 L logical circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-20 | 1984-07-21 | 1985-01-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-20 | 1988-07-21 | 1989-01-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-20 | 1992-07-21 | 1993-01-20 | $7700.00 | Window Closed / Lapsed |