Patent US4245305A successfully refreshed from Google Patents.
US4245305A
Expired / Lapsed
US
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Direct memory access control device
Assignee: TIM SpA
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Filing: 1978-12-20
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Granted: 1981-01-13
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Expires: 1998-12-20
Abstract
Abstract In a computer wherein a central processor and at least one peripheral controller have access to a memory, this latter is divided into two simultaneously accessible zones, namely a private zone accessible by the processor and a direct access zone accessible both by the processor and by the peripheral controller. A logic unit synchronizes the controller's access to the direct access zone with the processor's access to the private zone, the controller's access being delayed, if necessary to occur simultaneously with the processor's access. The peripheral controller's access is thereby achieved without interruption of processor operations.
Inventors
- 👤 Walter Gechele
- 👤 Vincenzo Casolino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:46
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G06F13/20; G06F13/28; G06F13/287
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
185 words
A computer comprising a central processor, at least one peripheral unit controller, a memory connected to said central processor and to said controller for storing data and instructions, said processor and said controller being selectively conditionable for executing a correspondent input-output access cycle to said memory for storing or reading out said data and instructions, and a controlling logic unit for so conditioning said processor and said controller, wherein the improvement comprises: first access control means conditionable by said central processor for causing a first zone of said memory to be accessed soley by said control processor, second access control means conditionable by said logic unit for causing a second zone of said memory to be accessed by said controller and said central processor separately with respect to the access to said first zone selectively by said processor, and synchronizing means included in said logic unit and conditioned by said second access control means, when said controller is accessed for synchronizing the access of said controller to said second zone with the access of said processor to said first zone as to be effected simultaneously.
Claim 2
Dependent Claim
185 words
A computer comprising a central processor, at least one peripheral unit controller, a memory connected to said central processor and to said controller for storing data and instructions, said processor and said controller being selectively conditionable for executing a correspondent input-output access cycle to said memory for storing or reading out said data and instructions, and a controlling logic unit for so conditioning said processor and said controller, wherein the improvement comprises: first access control means conditionable by said central processor for causing a first zone of said memory to be accessed soley by said control processor, second access control means conditionable by said logic unit for causing a second zone of said memory to be accessed by said controller and said central processor separately with respect to the access to said first zone selectively by said processor, and synchronizing means included in said logic unit and conditioned by said second access control means, when said controller is accessed for synchronizing the access of said controller to said second zone with the access of said processor to said first zone as to be effected simultaneously.
Claim 3
Dependent Claim
96 words
A computer according to claim 1 wherein said first access control means comprises a first communication channel connecting said processor to said first memory zone and said second access control means comprises a second communication channel connecting the processor to said second memory zone and a third communication channel connecting the controller to said second memory zone, said logic unit comprising means responsive to a signal of said processor indicating its access to said first memory zone and to a signal of said controller indicating access to said second memory zone for conditioning said synchronizing means.
Claim 4
Dependent Claim
81 words
A computer according to claim 1 further comprising request means connected to said peripheral unit controller for producing a request signal which is transmitted to said logic unit to represent the request of said controller for an access cycle to said second memory zone, and priority means included in said logic unit and controlled by said request signal for inhibiting the access to said second memory zone by said processor during the access cycle to said second zone by said controller.
Claim 5
Dependent Claim
56 words
A computer according to claim 3, wherein said controlling logic unit comprises means for delaying said access by the peripheral unit controller in such manner as to synchronise the beginning of said access by the controller to the second memory zone with the beginning of an access by the central processor to said first memory zone.
Claim 6
Dependent Claim
119 words
A computer according to claim 4 including a plurality of peripheral unit controllers, said request means being connected to all said controllers, said priority means comprising a circuit adapted to distinguish a first of said requests of access from following requests consecutively coming from said controllers during the time that said second memory zone is accessed by one of said controllers, and deactivating means responsive to said circuit for deactivating said delay means whenever said following requests are detected, whereby only the cycle of access requested by said first request of said controllers is delayed by said delaying means, the cycle of access requested by said following requests being allowed by said logic unit consecutively to said first cycle.
Claim 7
Dependent Claim
53 words
A computer according to claim 8, further comprising manually settable means for setting the capacity and location of the said first zone and said second zone of the memory, and means for indicating to which of said zones the request for access by the central processor and by said peripheral controller is referred.
Claim 8
Dependent Claim
96 words
A computer according to claim 6, comprising first and second addressing means associated to said first and said second memory zone, a first and a second circuit for recognizing when an address generated by said first and second addressing means are not found in the respective memory zone, and connecting means included in said logic unit and controlled by said indicating means for selectively connecting said recognizing circuits to said processors to prevent the operations of said access control means when the memory zone for which access is requested is not consistent with the generated address.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-13 | 1984-07-14 | 1985-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-13 | 1988-07-14 | 1989-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-13 | 1992-07-14 | 1993-01-13 | $7700.00 | Window Closed / Lapsed |