Method of digital control of m-phase thyristor-pulse d-c converters and apparatus for effecting same

Claim 1

A method of digital control of thyristors of m-phase thyristor-pulse d-c converters, comprising: generating time-shifted and time-constant pulse trains in each of "m" control channels within the control zone of each control channel; successively connecting each of said control channels to said thyristors of a respective phase of said m-phase thyristor-pulse converter upon achieving the maximum limit of the control zone for each of said control channels within the entire control zone; and changing the duration of the conductive state of said thyristors by feeding them with said pulse trains from each control channel, while simultaneously shifting the onset of operation of each said phase of said m-phase thyristor-pulse d-c converter by (1/m)T, where m is the number of phases of the thyristor-pulse d-c converter and T is the switching period of said thyristors.

Claim 2

A method of digital control of thyristors of m-phase thyristor-pulse d-c converters, comprising: generating time-shifted and time-constant pulse trains in each of "m" control channels within the control zone of each control channel; successively connecting each of said control channels to said thyristors of a respective phase of said m-phase thyristor-pulse converter upon achieving the maximum limit of the control zone for each of said control channels within the entire control zone; and changing the duration of the conductive state of said thyristors by feeding them with said pulse trains from each control channel, while simultaneously shifting the onset of operation of each said phase of said m-phase thyristor-pulse d-c converter by (1/m)T, where m is the number of phases of the thyristor-pulse d-c converter and T is the switching period of said thyristors.

Claim 3

An apparatus for digital control of m-phase thyristor-pulse converters, comprising; a master oscillator; a clock pulse counting unit including a single clock counter; a decoder for decoding time-constant pulse trains; decoders for decoding tim-shifted pulse trains, each decoder having logic inputs and data inputs; a decoder for decoding the l-th time-shifted pulse train, each of said decoders for decoding the l-th time-shifted pulse train including a decoding matrix whose inputs are connected to the inputs of an OR gate; a switching unit made as a bidirectional counter having an add input, a substract input, data outputs, control outputs, and an l-th control output; a control unit whose outputs are connected to said add and substract inputs of said bidirectional counter, said data outputs of said switching unit being connected to said data inputs of each of the decoders of the l-th time-shifted pulse train, said logic inputs of each of the decoders for decoding said l-th time-shifted pulse train being connected to the inputs of said decoder for decoding time-constant pulse trains, an output of said master oscillator being connected to the input of said clock counter; a control device also including a matching unit comprising: "m" groups of AND gates with "m" AND gates in each group; a first group of AND gates; l-th, m-th, p-th, k-th groups of AND gates; a first AND gate in each of said groups of AND gates and m-th, l-th, k-th, i-th, and j-th AND gates in each of said groups, an input of said l-th AND gate in each of said groups being connected to the output of said decoder for decoding the l-th time-shifted pulse trains, each of said AND gates of said l-th group being connected to the l-th output of said control outputs of said bidirectional counter, said matching unit having "m" outputs, including an l-th output, an (m-p+2)-th output, an (m-p+/1)-th output, a (k+l)-th output, an (m+i-k+l)-th output, and a (j-k+l)-th output, an output of said l-th AND gate in said first group serving as said l-th output of said matching unit, an output of said first AND gate in said p-th group serving as said (m-p+2)-th output of said matching unit, an output of said m-th AND gate in said p-th group serving as said (m-p+1)-th output of said matching unit, an output of said k-th AND gate in said m-th group serving as said (k+l)-th output of said matching unit, and outputs of said i-th and j-th AND gates in said k-th group serving, respectively, as said (m+1-k+1)-th and (j-k+l)-th outputs of said matching unit, where l=1,2, . . . m, p=2,3 . . . m, k=2,3, . . . (m-1), i=2,3, . . . k-1, j=k, . . . k+1, . . . m-1.

Claim 4

An apparatus for digital control of m-phase thyristor-pulse converters, comprising; a master oscillator; a clock pulse counting unit including a single clock counter; a decoder for decoding time-constant pulse trains; decoders for decoding tim-shifted pulse trains, each decoder having logic inputs and data inputs; a decoder for decoding the l-th time-shifted pulse train, each of said decoders for decoding the l-th time-shifted pulse train including a decoding matrix whose inputs are connected to the inputs of an OR gate; a switching unit made as a bidirectional counter having an add input, a substract input, data outputs, control outputs, and an l-th control output; a control unit whose outputs are connected to said add and substract inputs of said bidirectional counter, said data outputs of said switching unit being connected to said data inputs of each of the decoders of the l-th time-shifted pulse train, said logic inputs of each of the decoders for decoding said l-th time-shifted pulse train being connected to the inputs of said decoder for decoding time-constant pulse trains, an output of said master oscillator being connected to the input of said clock counter; a control device also including a matching unit comprising: "m" groups of AND gates with "m" AND gates in each group; a first group of AND gates; l-th, m-th, p-th, k-th groups of AND gates; a first AND gate in each of said groups of AND gates and m-th, l-th, k-th, i-th, and j-th AND gates in each of said groups, an input of said l-th AND gate in each of said groups being connected to the output of said decoder for decoding the l-th time-shifted pulse trains, each of said AND gates of said l-th group being connected to the l-th output of said control outputs of said bidirectional counter, said matching unit having "m" outputs, including an l-th output, an (m-p+2)-th output, an (m-p+/1)-th output, a (k+l)-th output, an (m+i-k+l)-th output, and a (j-k+l)-th output, an output of said l-th AND gate in said first group serving as said l-th output of said matching unit, an output of said first AND gate in said p-th group serving as said (m-p+2)-th output of said matching unit, an output of said m-th AND gate in said p-th group serving as said (m-p+1)-th output of said matching unit, an output of said k-th AND gate in said m-th group serving as said (k+l)-th output of said matching unit, and outputs of said i-th and j-th AND gates in said k-th group serving, respectively, as said (m+1-k+1)-th and (j-k+l)-th outputs of said matching unit, where l=1,2, . . . m, p=2,3 . . . m, k=2,3, . . . (m-1), i=2,3, . . . k-1, j=k, . . . k+1, . . . m-1.

Claim 5

A method for controlling thyristors of m-phase thyristor-pulse d.c. converters, wherein the duration of the conductive state of the thyristors in each phase of the m-phase thyristor-pulse converter is changed by an identical amount within the thyristor switching period (T) comprising the steps of supplying some of the thyristors with trains of time-shifted pulses and other thyristors with trains of time-constant pulses shaped in each of the control channels, and simultaneously shifting the beginning of operation of the thyristors in each phase by 1/m T relative to each other, and successively connecting each channel where the time-shifted trains of pulses are shaped to the respective phases of the converter as the duration of the conductive state of thyristors in each phase changes within the entire control range after the duration of the conductive state of the thyristors has reached a level equal to 1/m T, a corresponding level of the channel control zone.

Claim 6

A method for controlling thyristors of m-phase thyristor-pulse d.c. converters, wherein the duration of the conductive state of the thyristors in each phase of the m-phase thyristor-pulse converter is changed by an identical amount within the thyristor switching period (T) comprising the steps of supplying some of the thyristors with trains of time-shifted pulses and other thyristors with trains of time-constant pulses shaped in each of the control channels, and simultaneously shifting the beginning of operation of the thyristors in each phase by 1/m T relative to each other, and successively connecting each channel where the time-shifted trains of pulses are shaped to the respective phases of the converter as the duration of the conductive state of thyristors in each phase changes within the entire control range after the duration of the conductive state of the thyristors has reached a level equal to 1/m T, a corresponding level of the channel control zone.