US4244018A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interlock control of asynchronous data transmission between a host processor and a plurality of microprocessors through a common buffer
Assignee: AG Communication Systems Corp
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Filing: 1978-05-15
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Granted: 1981-01-06
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Expires: 1998-05-15
Abstract
Abstract An interlock circuit is set forth which provides for controlling asynchronous data transfers between a host processor and a plurality of microprocessors via a common buffer. The interlock circuit consists of an interconnection of latches arranged so that the first processor initiating a transfer request inhibits all remaining processors from activating their respective transfer requests. Each processor upon terminating a data transfer clears its associated transfer request. The host processor can clear all transfer requests upon command.
Inventors
- 👤 Wing F. Mui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:38
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/167; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/364
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
243 words
An interlock circuit providing for bidirectional control of asynchronous data transfer , via a common buffer element, between a host processor operable to transmit a transfer request signal and at least one of two microprocessors each operable to transmit a transfer request signal when said processors are in operation to transfer data between any two of said processors, said interlock circuit comprising: first latching means connected to said host processor and normally operated in response to said transfer request signal transmitted from said host processor to store and acknowledge said request signal; second latching means connected to a first microprocessor and connected to said first latching means and normally operated in response to said transfer request signal transmitted from said first microprocessor to store and acknowledge said request signal; and third latching means connected to a second microprocessor and connected to said first and to said second latching means and normally operated in response to said transfer request signal transmitted from said second microprocessor to store and acknowledge said request signal; said storage and acknowledgement of said transfer request signal from a first one of said processors to transmit its transfer request signal being effective to inhibit acceptance and acknowledgement of said transfer request signals from any other processors by inhibiting said transmission of signals acknowledging acceptance and storage of said transfer request signals of said other processors, whereby attempted simultaneous data transfer through said buffer element is controlled by said interlock circuit.
Claim 2
Dependent Claim
243 words
An interlock circuit providing for bidirectional control of asynchronous data transfer , via a common buffer element, between a host processor operable to transmit a transfer request signal and at least one of two microprocessors each operable to transmit a transfer request signal when said processors are in operation to transfer data between any two of said processors, said interlock circuit comprising: first latching means connected to said host processor and normally operated in response to said transfer request signal transmitted from said host processor to store and acknowledge said request signal; second latching means connected to a first microprocessor and connected to said first latching means and normally operated in response to said transfer request signal transmitted from said first microprocessor to store and acknowledge said request signal; and third latching means connected to a second microprocessor and connected to said first and to said second latching means and normally operated in response to said transfer request signal transmitted from said second microprocessor to store and acknowledge said request signal; said storage and acknowledgement of said transfer request signal from a first one of said processors to transmit its transfer request signal being effective to inhibit acceptance and acknowledgement of said transfer request signals from any other processors by inhibiting said transmission of signals acknowledging acceptance and storage of said transfer request signals of said other processors, whereby attempted simultaneous data transfer through said buffer element is controlled by said interlock circuit.
Claim 3
Dependent Claim
88 words
An interlock circuit as claimed in claim 1, wherein: said first latching means includes enabling means connected to said host processor and normally operated in response to said transfer request signal; and said first latching means further includes a first latch connected to said enabling means and to said host processor wherein said first latch is operated in response to said operation of said enabling means to store said host processor's transfer request signal and to acknowledge to said host processor the storage of said transfer request signal.
Claim 4
Dependent Claim
147 words
An interlock circuit as claimed in claim 2, wherein: said second latching means includes enabling means connected to said first microprocessor and to said first latch and normally operated in response to said transfer request signal of said first microprocessor and in the absence of a latched transfer request signal in the first latch; and said second latching means further includes a second latch connected to said enabling means, to said first microprocessor and to said enabling means of said first latching means wherein said second latch is operated in response to said operation of said enabling means to store said first microprocessor's transfer request signal, to acknowledge to said first microprocessor the storage of the transfer request in said second latch, and to inhibit the acceptance of the transfer request signal by said first latching means when said first microprocessor is the first one to operate.
Claim 5
Dependent Claim
71 words
An interlock circuit as claimed in claim 3, wherein: said second latching means further includes combining means connected to said second latch, to said host processor and to said first microprocessor, wherein said combining means is operated in response to clear signals of said host processor and said first microprocessor whereby said transfer request signal of said first microprocessor is cleared from its said stored state by resetting said second latch.
Claim 6
Dependent Claim
160 words
An interlock circuit as claimed in claim 3, wherein: said third latching means includes enabling means connected to said second microprocessor and to said first and second latches and operated in response to said transfer request signal of said second microprocessor and in the absence of a latched transfer request signal in the first and second latches; and said third latching means further includes a third latch connected to said enabling means of said third latching means and to said second microprocessor and to said enabling means of said first and said second latching means, and said third latch operated in response to said operation of said enabling means to store said second microprocessor's transfer request signal to acknowledge to said second microprocessor the storage of the transfer request in the third latch, and to inhibit the acceptance of the transfer request signal by the first and second latching means when said second processor is the first one to operate.
Claim 7
Dependent Claim
71 words
An interlock circuit as claimed in claim 5, wherein: said third latching means further includes combined means connected to said third latch, to said host processor and to said second microprocessor, wherein said combining means is operated in response to clear signals of said host processor and said second microprocessor whereby said transfer request signal of said second microprocessor is cleared from its said stored state by resetting said third latch.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-06 | 1984-07-07 | 1985-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-06 | 1988-07-07 | 1989-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-06 | 1992-07-07 | 1993-01-06 | $7700.00 | Window Closed / Lapsed |