Capacitor memory and methods for reading, writing, and fabricating capacitor memories

Claim 2

The process of writing in a capacitor memory array, the array comprising a plurality of isolated capacitor cells, each cell including at least a first conductive layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor layer, and a second conductive layer, the first conductive layers of said cells being grouped and interconnected into a plurality of word lines and the second conductive layers of said cells being grouped and interconnected into a plurality of bit lines, one each of said bit and word lines uniquely identifying a capacitor cell, and each cell having two capacitor states, the process including the steps of applying to at least one selected cell of said memory array a first potential (a) having a polarity to drive a portion of the substrate of said cell into depletion, (b) having a sufficient magnitude to effect avalanche breakdown in said depletion portion of the substrate of said cell, and (c) having sufficient magnitude and duration to change the state of said cell and simultaneously applying to unselected cells of said memory array at least a second potential having a magnitude and duration insufficient to change a state of said unselected cells.

Claim 3

The process of writing in a capacitor memory according to claim 1 wherein said avalanche breakdown occurs at a voltage which is comparable to the magnitude of write voltage of said memory wherein said polarity is in the accumulation direction.

Claim 4

The process of writing of claim 1 wherein the duration of said first potential is less than 100 microseconds.

Claim 5

The process of writing of claim 1 wherein the duration of said first potential is less than 1 microsecond.

Claim 6

The process of writing in a capacitor memory array, the memory comprising a plurality of isolated capacitor cells arranged in a rectilinear pattern, each capacitor cell exhibiting a capacitance versus applied potential hysteresis under the effect of an applied potential, including the steps of A. simultaneously (1) applying a first potential across each capacitor cell within a selected portion of the memory array, the potential having a polarity to drive a substrate portion of each capacitor cell of said selected portion into accumulation and the magnitude and duration of said first potential being sufficient to change the flat-band voltage of each capacitor cell, and (2) applying across each unselected cell of said memory array potentials insufficient in magnitude and duration to change the flat-band voltage of the unselected cells, and B. thereafter, simultaneously (1) applying across each cell of a second selected portion, a second potential having a polarity opposite that of the first potential and having sufficient magnitude and duration to (a) effect avalanche breakdown in a substrate portion of each cell of said second selected portion and (b) change the flat-band voltage of said selected capacitor cells and (2) applying across each unselected cell of said memory array potentials of a magnitude and duration insufficient to change the flat-band voltage of the second unselected cells.

Claim 7

The process of writing in a capacitor memory array, the memory comprising a plurality of isolated capacitor cells arranged in a rectilinear pattern, each capacitor cell exhibiting a capacitance versus applied potential hysteresis under the effect of an applied potential, including the steps of A. simultaneously (1) applying a first potential across each capacitor cell within a selected portion of the memory array, the potential having a polarity to drive a substrate portion of each capacitor cell of said selected portion into accumulation and the magnitude and duration of said first potential being sufficient to change the flat-band voltage of each capacitor cell, and (2) applying across each unselected cell of said memory array potentials insufficient in magnitude and duration to change the flat-band voltage of the unselected cells, and B. thereafter, simultaneously (1) applying across each cell of a second selected portion, a second potential having a polarity opposite that of the first potential and having sufficient magnitude and duration to (a) effect avalanche breakdown in a substrate portion of each cell of said second selected portion and (b) change the flat-band voltage of said selected capacitor cells and (2) applying across each unselected cell of said memory array potentials of a magnitude and duration insufficient to change the flat-band voltage of the second unselected cells.

Claim 8

The process of writing of claim 5 wherein said second potential has a magnitude approximately twice the magnitude of the first potential.

Claim 9

The process of writing of claim 5 wherein one of said insufficient potentials is zero volts.

Claim 10

The process of writing of claim 5 wherein at least one of said insufficient potentials drives substrate portion of said unselected capacitor cells in the depletion direction.

Claim 11

The process of writing in a metal-nitride-oxide-silicon capacitor memory array, the memory comprising a plurality of isolated capacitor cells arranged in a rectilinear pattern, including the steps of A. simultaneously (1) applying a first potential across each cell in a selected portion of the memory array, the potential having a polarity to drive a substrate portion of each capacitor cell of said selected portion into accumulation, the potential having a magnitude and duration sufficient to change the flat-band voltage of each selected capacitor cell, and (2) applying across each unselected cell of said memory array potentials insufficient in magnitude and duration to change the flat-band voltage of the unselected cells, and B. thereafter, simultaneously (1) applying across each cell of a second selected portion, a second potential having a polarity opposite that of the first potential and having sufficient magnitude and duration to (a) effect avalanche breakdown in said substrate and (b) change the flat-band voltage of each cell of said selected portion and (2) applying to each unselected second cell potentials of a magnitude and duration insufficient to change the flat-band voltage of each cell of said unselected second cells.

Claim 12

The process of writing in a metal-nitride-oxide-silicon capacitor memory array, the memory comprising a plurality of isolated capacitor cells arranged in a rectilinear pattern, including the steps of A. simultaneously (1) applying a first potential across each cell in a selected portion of the memory array, the potential having a polarity to drive a substrate portion of each capacitor cell of said selected portion into accumulation, the potential having a magnitude and duration sufficient to change the flat-band voltage of each selected capacitor cell, and (2) applying across each unselected cell of said memory array potentials insufficient in magnitude and duration to change the flat-band voltage of the unselected cells, and B. thereafter, simultaneously (1) applying across each cell of a second selected portion, a second potential having a polarity opposite that of the first potential and having sufficient magnitude and duration to (a) effect avalanche breakdown in said substrate and (b) change the flat-band voltage of each cell of said selected portion and (2) applying to each unselected second cell potentials of a magnitude and duration insufficient to change the flat-band voltage of each cell of said unselected second cells.

Claim 13

The process of writing in a capacitor memory array, the array comprising a plurality of isolated capacitor cells, each cell including at least a first conductive layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor layer, and a second conductive layer, the first conductive layers of said cells being grouped and interconnected into a plurality of word lines and the second conductive layers of said cells being grouped and interconnected into a plurality of bit lines, one each of said bit and word lines uniquely identifying a capacitor cell, and each cell having first and second capacitor states, the process including the steps of simultaneously A. applying to a word line connected to each selected cell of said memory array a first potential, B. applying to bit lines connected to said selected cells a second potential, said first and second potentials driving a portion of the substrate of said selected cells into depletion, said potentials providing a sufficient potential difference across the selected cells to effect avalanche breakdown in said depletion portion of the substrate of said selected cells, and said potentials having a sufficient potential difference and time duration to change the state of said selected cells to said second capacitor state, C. applying to each other word line of said memory array a third potential to inhibit a change of state of unselected cells connected to said bit lines, D. applying a fourth potential to each other bit line of said memory array to inhibit a change of state of unselected cells connected to said word line, and E. choosing said third and fourth potentials so that each cell connected between one of said other word lines and one of said other bit lines is inhibited from changing its state.

Claim 14

The process of writing in a capacitor memory array, the array comprising a plurality of isolated capacitor cells, each cell including at least a first conductive layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor layer, and a second conductive layer, the first conductive layers of said cells being grouped and interconnected into a plurality of word lines and the second conductive layers of said cells being grouped and interconnected into a plurality of bit lines, one each of said bit and word lines uniquely identifying a capacitor cell, and each cell having first and second capacitor states, the process including the steps of simultaneously A. applying to a word line connected to each selected cell of said memory array a first potential, B. applying to bit lines connected to said selected cells a second potential, said first and second potentials driving a portion of the substrate of said selected cells into depletion, said potentials providing a sufficient potential difference across the selected cells to effect avalanche breakdown in said depletion portion of the substrate of said selected cells, and said potentials having a sufficient potential difference and time duration to change the state of said selected cells to said second capacitor state, C. applying to each other word line of said memory array a third potential to inhibit a change of state of unselected cells connected to said bit lines, D. applying a fourth potential to each other bit line of said memory array to inhibit a change of state of unselected cells connected to said word line, and E. choosing said third and fourth potentials so that each cell connected between one of said other word lines and one of said other bit lines is inhibited from changing its state.

Claim 15

The process of writing of claim 10 wherein said substrate is an "N" type silicon semiconductor, said first potential is negative, said second potential is positive, and said third and fourth potentials are each zero.

Claim 16

The process of writing of claim 11 wherein said first and second potentials are equal in magnitude.

Claim 17

The process of writing of claim 10 wherein an unselected cell connected to said word line is in depletion.

Claim 18

The processing of writing of claim 13 wherein an unselected cell connected to one of said bit lines is in depletion.

Claim 19

The process of writing of claim 14 wherein said first and fourth potentials have a first potential difference and said second and third potentials have a second potential difference, said first and second potential differences each being substantially equal in magnitude to an avalanche breakdown voltage for said substrate.

Claim 20

The process of writing of claim 10 wherein there is zero potential across each cell connected between said other bit lines and other word lines.

Claim 21

The process of writing of claim 10 wherein said substrate is a "P" type silicon semiconductor, said first potential is positive, said second potential is negative, and said third and fourth potentials are each zero.

Claim 22

The process of writing of claim 17 wherein said first and second potentials are equal in magnitude.

Claim 23

The process of writing of claim 10 wherein all of said potentials are nonnegative.

Claim 24

The process of writing of claim 10 wherein all of said potentials are nonpositive.

Claim 25

The process of writing in a capacitor memory array, the array comprising a plurality of isolated capacitor cells, each cell including at least a first conductive layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor layer, and a second conductive layer, the first conductive layers of said cells being grouped and interconnected into a plurality of word lines and the second conductive layers of said cells being grouped and interconnected into a plurality of bit lines, one each of said bit and word lines uniquely identifying a capacitor cell, and each cell having first and second capacitor states, the process including the steps of simultaneously A. applying to a word line connected to each selected cell of said memory array a first potential, B. applying to bit lines connected to said selected cells a second potential, said first and second potentials driving a portion of the substrate of said selected cells into accumulation, and said potentials having a sufficient potential difference and time duration to change the state of said selected cells to the first capacitor state, C. applying to each other word line of said memory array a third potential to inhibit a change of state of unselected cells connected to said bit lines, D. applying a fourth potential to each other bit line of said memory array to inhibit a change of state of unselected cells connected to said word line, and E. choosing said third and fourth potentials so that each cell connected between one of said other word lines and one of said other bit lines is inhibited from changing its state and said third and fourth potentials having a potential difference substantially equal in magnitude to an avalanche breakdown voltage for said substrate.

Claim 26

The process of writing in a capacitor memory array, the array comprising a plurality of isolated capacitor cells, each cell including at least a first conductive layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor layer, and a second conductive layer, the first conductive layers of said cells being grouped and interconnected into a plurality of word lines and the second conductive layers of said cells being grouped and interconnected into a plurality of bit lines, one each of said bit and word lines uniquely identifying a capacitor cell, and each cell having first and second capacitor states, the process including the steps of simultaneously A. applying to a word line connected to each selected cell of said memory array a first potential, B. applying to bit lines connected to said selected cells a second potential, said first and second potentials driving a portion of the substrate of said selected cells into accumulation, and said potentials having a sufficient potential difference and time duration to change the state of said selected cells to the first capacitor state, C. applying to each other word line of said memory array a third potential to inhibit a change of state of unselected cells connected to said bit lines, D. applying a fourth potential to each other bit line of said memory array to inhibit a change of state of unselected cells connected to said word line, and E. choosing said third and fourth potentials so that each cell connected between one of said other word lines and one of said other bit lines is inhibited from changing its state and said third and fourth potentials having a potential difference substantially equal in magnitude to an avalanche breakdown voltage for said substrate.

Claim 27

The process of writing of claim 21 wherein the potential difference between the third and fourth potentials is equal to the avalanche breakdown voltage.

Claim 28

The process of writing of claim 21 wherein the first and fourth potentials are equal and the second and third potentials are equal.

Claim 29

The process of writing of claim 21 wherein each cell connected between said other word lines and said other bit lines is in depletion.

Claim 30

The process of writing of claim 24 wherein each other unselected cell has a zero potential across it.

Claim 31

The process of reading a selected cell of a capacitor memory array, the array comprising a plurality of isolated capacitor cells, each cell including at least a first conductive layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor layer, and a second conductive layer, the first conductive layers of said cells being grouped and interconnected into a plurality of word lines and the second conductive layers of said cells being grouped and interconnected into a plurality of digit lines, one each of said digit and word lines uniquely identifying a capacitor cell, and each cell having two capacitance states, the process including the steps of applying a variable potential between the word and digit lines identifying the selected cell, said variable potential having a voltage range extending at least in part across a "flat-band" portion of a known voltage-capacitance relationship for said cell, the maximum magnitude of said variable potential being sufficiently small so that the state of said selected cell is not changed, measuring the current flowing through said selected capacitor cell as a function of said voltage versus time, and determining the state of said capacitor cell from the shape of the current versus time profile.

Claim 32

The process of reading a selected cell of a capacitor memory array, the array comprising a plurality of isolated capacitor cells, each cell including at least a first conductive layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor layer, and a second conductive layer, the first conductive layers of said cells being grouped and interconnected into a plurality of word lines and the second conductive layers of said cells being grouped and interconnected into a plurality of digit lines, one each of said digit and word lines uniquely identifying a capacitor cell, and each cell having two capacitance states, the process including the steps of applying a variable potential between the word and digit lines identifying the selected cell, said variable potential having a voltage range extending at least in part across a "flat-band" portion of a known voltage-capacitance relationship for said cell, the maximum magnitude of said variable potential being sufficiently small so that the state of said selected cell is not changed, measuring the current flowing through said selected capacitor cell as a function of said voltage versus time, and determining the state of said capacitor cell from the shape of the current versus time profile.

Claim 33

The process of claim 26 wherein said second dielectric layer is a silicon dioxide layer.

Claim 34

The process of claim 26 wherein said variable potential is a voltage ramp, the time duration of said voltage ramp being significantly less than an RC time constant of the system being read.

Claim 35

The process of claim 28 wherein said voltage ramp is varied in the direction of depletion.

Claim 36

The process of claim 26 wherein said determining step includes the steps of measuring a change of amplitude of said current versus time signal and estimating from any amplitude jumps in said signal the state of the capacitor being read.

Claim 37

The process of claim 26 wherein said measuring step includes the steps of placing a resistor in a series circuit connection with the selected cell, and measuring the voltage drop across said resistor.

Claim 38

The process of reading a metal-nitride-oxide-silicon capacitor memory array having a plurality of digit lines and a plurality of word lines, and said memory including a plurality of cells, each cell having a plurality of charge states, including the steps of applying a variable potential across the word line and digit line identifying a selected cell, said variable potential extending at least in part across a "flat-band" portion of a known voltage-capacitance relationship for said cell, the maximum magnitude of said variable potential being sufficiently small so that a charge stored in said selected cell is not substantially changed, measuring the current flowing through said selected capacitor cell as a function of said voltage versus time, and determining the state of said capacitor cell by the shape of the current versus time profile.

Claim 39

The process of reading a metal-nitride-oxide-silicon capacitor memory array having a plurality of digit lines and a plurality of word lines, and said memory including a plurality of cells, each cell having a plurality of charge states, including the steps of applying a variable potential across the word line and digit line identifying a selected cell, said variable potential extending at least in part across a "flat-band" portion of a known voltage-capacitance relationship for said cell, the maximum magnitude of said variable potential being sufficiently small so that a charge stored in said selected cell is not substantially changed, measuring the current flowing through said selected capacitor cell as a function of said voltage versus time, and determining the state of said capacitor cell by the shape of the current versus time profile.

Claim 40

The process of claim 32 wherein said variable potential is a voltage ramp, said voltage ramp having a time duration significantly less than an RC time constant of the system being read.

Claim 41

The process of claim 33 wherein said voltage is varied in the direction of depletion.