US4241455A — Data receiving and processing circuit

Claim 1

Independent Claim 278 words

A circuit for processing weak light signals representative of digital data of the type having variable duty cycles comprising: an optical light detector for detecting said digital data light signal, said light signals having an A.C. signal component and a D.C. signal component resulting from a duty cycle other than a fifty percent duty cycle, a high-gain preamplifier coupled to said optical light detector for amplifying said A.C. and said D.C. signal components, said high-grain preamplifier further providing a second amplified D.C. component signal introduced by said preamplifier, a filter connected to the output of said preamplifier for removing both of said D.C. voltage component signals and for producing a floating A.C. voltage signal output, a linear amplifier coupled to said preamplifier for amplifying said floating A.C. voltage signal, a positive peak detector coupled to said amplified floating A.C. voltage signal for producing a substantially positive floating D.C. voltage representation of the positive peaks of said floating A.C. voltage signal, a negative peak detector coupled to said amplified floating A.C. voltage signal for producing a substantially negative floating D.C. voltage representation of the negative peaks of said floating A.C. voltage signal, a voltage divider having its two end terminals connected across the positive and the negative floating D.C. voltages which are representative of the peak outputs from said peak detectors, said voltage divider having an intermediate voltage tap representative of a predetermined voltage on said voltage divider, and a comparator having a first input connected to said intermediate voltage tap of said voltage divider and the other input connected to said floating amplified A.C. voltage signals for producing a voltage output signal representative of said original digital data.

Claim 2

Dependent Claim 278 words

A circuit for processing weak light signals representative of digital data of the type having variable duty cycles comprising: an optical light detector for detecting said digital data light signal, said light signals having an A.C. signal component and a D.C. signal component resulting from a duty cycle other than a fifty percent duty cycle, a high-gain preamplifier coupled to said optical light detector for amplifying said A.C. and said D.C. signal components, said high-grain preamplifier further providing a second amplified D.C. component signal introduced by said preamplifier, a filter connected to the output of said preamplifier for removing both of said D.C. voltage component signals and for producing a floating A.C. voltage signal output, a linear amplifier coupled to said preamplifier for amplifying said floating A.C. voltage signal, a positive peak detector coupled to said amplified floating A.C. voltage signal for producing a substantially positive floating D.C. voltage representation of the positive peaks of said floating A.C. voltage signal, a negative peak detector coupled to said amplified floating A.C. voltage signal for producing a substantially negative floating D.C. voltage representation of the negative peaks of said floating A.C. voltage signal, a voltage divider having its two end terminals connected across the positive and the negative floating D.C. voltages which are representative of the peak outputs from said peak detectors, said voltage divider having an intermediate voltage tap representative of a predetermined voltage on said voltage divider, and a comparator having a first input connected to said intermediate voltage tap of said voltage divider and the other input connected to said floating amplified A.C. voltage signals for producing a voltage output signal representative of said original digital data.

Claim 3

Dependent Claim 64 words

A circuit of the type set forth in claim 1 wherein said linear amplifier is provided with gain control inputs and there is further provided, an automatic gain control comprising a drive circuit having two inputs connected in parallel with said end terminals of said voltage divider, the output of said drive circuit being coupled to the gain control inputs of said linear amplifier.

Claim 4

Dependent Claim 69 words

A circuit of the type set forth in claim 2 which further includes a field effect transistor having its source and drain electrodes connected in series with the gain control inputs of said linear amplifier and its gate electrode connected to the output of said drive circuit, whereby, the effective gain of said linear amplifier is adjustable from a maximum gain with no feedback to the minimum gain limit.

Claim 5

Dependent Claim 36 words

A circuit of the type set forth in claim 3 which further includes a low frequency integrator connected in series between the output of said drive circuit and the gate electrode of said field effect transistor.

Claim 6

Independent Claim 168 words

A method of processing weak amplified original digital data signals of the type having an A.C. voltage signal component imposed on a D.C. voltage signal component comprising the steps of: amplifying said original data signals in a high gain amplifier which produces a second D.C. voltage signal component, filtering out the D.C. voltage signal components leaving a floating A.C. voltage signal component substantially intact, amplifying said floating A.C. voltage signal without introducing a substantial D.C. voltage signal component, detecting the positive and negative peaks of said floating A.C. voltage signal component, providing substantially D.C. voltage representation of said positive and said negative peaks of said floating A.C. voltage signal component, p1 applying said substantially D.C. voltage representations of said positive and said negative peaks across a voltage divider to provide a range of voltages intermediate said peak voltages, and applying said floating A.C. voltage signal component and an intermediate voltage from said voltage divider to a voltage comparator to provide an output representative of the original digital data.

Claim 7

Independent Claim 168 words

A method of processing weak amplified original digital data signals of the type having an A.C. voltage signal component imposed on a D.C. voltage signal component comprising the steps of: amplifying said original data signals in a high gain amplifier which produces a second D.C. voltage signal component, filtering out the D.C. voltage signal components leaving a floating A.C. voltage signal component substantially intact, amplifying said floating A.C. voltage signal without introducing a substantial D.C. voltage signal component, detecting the positive and negative peaks of said floating A.C. voltage signal component, providing substantially D.C. voltage representation of said positive and said negative peaks of said floating A.C. voltage signal component, p1 applying said substantially D.C. voltage representations of said positive and said negative peaks across a voltage divider to provide a range of voltages intermediate said peak voltages, and applying said floating A.C. voltage signal component and an intermediate voltage from said voltage divider to a voltage comparator to provide an output representative of the original digital data.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1983-12-23	1984-06-23	1984-12-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1987-12-23	1988-06-23	1988-12-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1991-12-23	1992-06-23	1992-12-23	$7700.00	Window Closed / Lapsed

Data receiving and processing circuit

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