Field effect transconductance amplifiers

Claim 2

A field effect device amplifier comprising first and second field effect devices each having source, drain and gate connections, said gate of said first field effect device being coupled to the amplifier input, said drain of said first field effect device being coupled to said source of said second field effect device and to the amplifier output, said amplifier also having means for substantially shorting said gate of said second field effect device to its said source for the intended operating frequency range of said amplifier, said field effect devices being biased to operate in a partial carrier velocity limited region, selected to provide a dependence of the output conductance of said field effect devices on drain current which approximates that of the transconductance of said field effect devices.

Claim 3

The amplifier of claim 1 wherein said means for substantially shorting said gate of said second field effect device to its said source comprises a capacitor.

Claim 4

The amplifier of claim 1 further comprised of means coupled between said drain of said second field effect device and said source of said first field effect device for setting the bias to said gate of said second field effect device.

Claim 5

The amplifier of claim 1 wherein said first field effect device comprises first and second field effect transistors coupled to form said first field effect device, each said field effect transistor having a gate, a drain and a source, said gate of said first field effect transistor forming said gate of said first field effect device, said source of said first field effect transistor and said gate of said second field effect transistor being coupled together to form said source of said first field effect device, and said drain of said second field effect transistor forming said drain of said first field effect device.

Claim 6

The amplifier of claim 4 wherein said second field effect device comprises third and fourth field effect transistors coupled to form said second field effect device, each said field effect transistor having a gate, a drain and a source, said gate of said third field effect transistor forming said gate of said second field effect device, said source of said third field effect transistor and said gate of said fourth field effect transistor being coupled together to form said source of said second field effect device, and said drain of said fourth field effect transistor forming said drain of said second field effect device.

Claim 7

The amplifier of claim 1 wherein at least one of said first and second field effect devices comprises a cascode connection of field effect transistors.

Claim 8

The amplifier of claim 6 wherein said cascode connection of field effect transistors comprises an AC cascode connection.

Claim 9

The amplifier of claim 6 wherein said cascode connection of field effect transistors comprises a DC cascode connection.

Claim 10

The amplifier of claim 6 wherein said cascode connection of field effect transistors comprises at least said first field effect device.

Claim 11

The amplifier of claim 1 wherein at least one of said first and second field effect devices comprises a stacked cascode connection of field effect transistors.

Claim 12

The amplifier of claim 10 wherein said stacked cascode comprises an AC stacked cascode.

Claim 13

The amplifier of claim 10 wherein said stacked cascode comprises a DC stacked cascode.

Claim 14

The amplifier of claim 10 wherein said stacked cascode connection of field effect transistors comprises at least said first field effect device.

Claim 15

The amplifier of claim 1 further comprised of at least third and fourth field devices, each having source, gate and drain connections, said first field effect device being coupled to said source of said third field effect device, said drain of said third field effect device being coupled to said source of said second field effect device and to the amplifier output, whereby said drain of said first field effect device is coupled to said source of said second field effect device through said third field effect device, said fourth field effect device having its source coupled to said drain of said second field effect device.

Claim 16

The amplifier of claim 14 wherein said third and fourth field effect devices also operate in a partial carrier velocity limited region, whereby the dependence of their output conductance on drain current is reduced to approximate that of their transconductance.

Claim 17

The amplifier of claim 15 further comprised of means for biasing said gates of said third and fourth field effect devices.

Claim 18

The amplifier of claim 15 wherein each of said third and fourth field effect devices has its said gate substantially shorted to its said source for the interested operating frequency range of said amplifier.

Claim 19

The amplifier of claim 1 further including gain control means comprised of means of controllably varying the drain current in said first and second field effect devices around the approximate value of drain current at which the dependence of the output conductance of said field effect devices on drain current is reduced to approximate that the transconductance of said field effect devices.

Claim 20

The amplifier of claim 1 wherein at least one of said field effect devices comprises a connection of field effect and bipolar transistors emulating a field effect device.

Claim 21

The amplifier of claim 19 wherein each of said field effect devices comprise a connection of field effect and bipolar transistors emulating the respective field effect.

Claim 22

A two stage field effect device amplifier comprising first, second, third and fourth field effect devices each having source, drain and gate connections, said gate of said first field effect device being coupled to the amplifier input, said drain of said first field effect device being coupled to said source of said second field effect device, said amplifier also having means for substantially shorting said gate of said second field effect device to its said source for the intended operating frequency range of said amplifier, said first and second field field effect devices being biased to operate in a partial carrier velocity limited region, whereby the dependence of the output conductance of said first and second field effect devices on drain current is reduced to approximate that of the transconductance of said field effect devices, said gate of said third field effect device being capacitively coupled to said drain of said first field effect device, said drain of said third field effect device being coupled to said source of said fourth field effect device and to the amplifier output, said amplifier also having means for substantially shorting said gate of said fourth field effect device to its said source for the intended operating frequency range of said amplifier, said third and fourth field effect devices being biased to operate in a partial carrier velocity limited region, whereby the dependence of the output conductance of said field effect devices on drain current is reduced to approximate that of the transconductance of said field effect devices, said drain of said first and said third field effect devices being coupled together through resistive means to provide feed-forward between stages.

Claim 23

A two stage field effect device amplifier comprising first, second, third and fourth field effect devices each having source, drain and gate connections, said gate of said first field effect device being coupled to the amplifier input, said drain of said first field effect device being coupled to said source of said second field effect device, said amplifier also having means for substantially shorting said gate of said second field effect device to its said source for the intended operating frequency range of said amplifier, said first and second field field effect devices being biased to operate in a partial carrier velocity limited region, whereby the dependence of the output conductance of said first and second field effect devices on drain current is reduced to approximate that of the transconductance of said field effect devices, said gate of said third field effect device being capacitively coupled to said drain of said first field effect device, said drain of said third field effect device being coupled to said source of said fourth field effect device and to the amplifier output, said amplifier also having means for substantially shorting said gate of said fourth field effect device to its said source for the intended operating frequency range of said amplifier, said third and fourth field effect devices being biased to operate in a partial carrier velocity limited region, whereby the dependence of the output conductance of said field effect devices on drain current is reduced to approximate that of the transconductance of said field effect devices, said drain of said first and said third field effect devices being coupled together through resistive means to provide feed-forward between stages.

Claim 24

A field effect device amplifier comprising first, second and third field effect devices each having source, drain and gate connections, said gate of said first field effect device being coupled to the amplifier input, said drain of said first field effect device being coupled to said source of said second field effect device and to the amplifier output, said amplifier also having means for substantially shorting said gate of said second field effect device to its said source for the intended operating frequency range of said amplifier, said source of said third field effect device being coupled to said drain of said second field effect device, said gate of said third field effect device being capacitively coupled to said source of said first field effect device, said source of said first field effect device and said drain of said third field effect device each being coupled to one power supply connection.

Claim 25

A field effect device amplifier comprising first, second and third field effect devices each having source, drain and gate connections, said gate of said first field effect device being coupled to the amplifier input, said drain of said first field effect device being coupled to said source of said second field effect device and to the amplifier output, said amplifier also having means for substantially shorting said gate of said second field effect device to its said source for the intended operating frequency range of said amplifier, said source of said third field effect device being coupled to said drain of said second field effect device, said gate of said third field effect device being capacitively coupled to said source of said first field effect device, said source of said first field effect device and said drain of said third field effect device each being coupled to one power supply connection.

Claim 26

The device of claim 22 wherein said first and second field effect devices are biased to operate in a partial carrier velocity limited region, whereby the dependence of the output conductance of said first and second field effect devices on drain current is reduced to approximate that of the transconductance of said field effect devices.

Claim 27

The device of claim 23 wherein said third field effect device is also biased to operate in a partial carrier velocity limited region, whereby the dependence of the output conductance of said third field effect device on drain current is reduced to approximate that of the transconductance of said field effect devices.

Claim 28

The amplifier of claim 22 wherein said means for substantially shorting said gate of said second field effect device to its said source comprises a capacitor.

Claim 29

The amplifier of claim 22 further comprised of means coupled between said drain of said second field effect device and said source of said first field effect device for setting the bias to said gate of said second field effect device.

Claim 30

The amplifier of claim 26 further comprised of means coupled between said source of said first field effect device and said drain of said third field effect device for setting the bias to said gate of said third field effect device.

Claim 31

The amplifier of claim 22 wherein said first field effect device comprises first and second field effect transistors coupled to form said first field effect device, each said field effect transistor having a gate, a drain and a source, said gate of said first field effect transistor forming said gate of said first field effect device, said source of said first field effect transistor and said gate of said second field effect transistor being coupled together to form said source of said first field effect device, and said drain of said second field effect transistor forming said drain of said first field effect device.

Claim 32

The amplifier of claim 28 wherein said second field effect device comprises third and fourth field effect transistors coupled to form said second field effect device, each said field effect transistor having a gate, a drain and a source, said gate of said third field effect transistor formed said gate of said second field effect device, said source of said third field effect transistor and said gate of said fourth field effect transistor being coupled together to form said source of said second field effect device, and said drain of said fourth field effect transistor forming said drain of said second field effect device.

Claim 33

The amplifier of claim 22 wherein at least one of said first and second field effect devices comprises a cascode connection of field effect transistors.

Claim 34

The amplifier of claim 30 wherein said cascode connection of field effect transistors comprises an AC cascode connection.

Claim 35

The amplifier of claim 22 wherein said cascode connection of field effect transistors comprises a DC cascode connection.

Claim 36

The amplifier of claim 32 wherein said cascode connection of field effect transistors comprises at least said first field effect device.

Claim 37

The amplifier of claim 22 wherein at least one of said first and second field effect devices comprises a stacked cascode connection of field effect transistors.

Claim 38

The amplifier of claim 34 wherein said stacked cascode comprises an AC stacked cascode.

Claim 39

The amplifier of claim 34 wherein said stacked cascode comprises a DC stacked cascode.

Claim 40

The amplifier of claim 34 wherein said stacked cascode connection of field effect transistors comprises at least said first field effect device.

Claim 41

The amplifier of claim 22 wherein at least one of said field effect devices comprises a connection of field effect and bipolar transistors emulating a field effect device.

Claim 42

The amplifier of claim 22 wherein each of said field effect devices comprise a connection of field effect and bipolar devices emulating the respective field effect.