Circuit using dynamic high impedance load

Claim 2

Am amplifying circuit consisting of three terminals with the first two terminals adapted to be connected to the source of signals to be amplified, a high dynamic impedance load connected to said third terminal, the output being taken from said load, at least three field effect transistors each having a control gate and two terminals across which the impedance is varied by said gate, one variable impedance terminal of the first transistor being connected to said high impedance load, the gate of said first transistor being connected to the first variable impedance terminal of said second transistor, the other variable impedance terminal of the first transistor being connected to the second variable impedance terminal of the second transistor, the gate of said second transistor being connected to the first variable impedance terminal of said third transistor, the first variable impedance terminal of said second transistor being connected to the second variable impedance terminal of said third transistor, and the first and second terminals being respectively connected to the gate and first variable impedance terminals of said third transistor.

Claim 3

An amplifying circuit as in claim 1 wherein said high dynamic impedance load consists of a resistor having first and second terminals with its first terminal connected to said first transistor as its input terminal, at least three load field effect transistors each having a control gate to vary the impedance across its two other variable impedance terminals, the gate of the first load field effect transistor being connected to said input terminal, a variable impedance terminal of said first load transistor being connected to said second resistor terminal and to the gate of said second load transistor, the other variable impedance terminal of the first load transistor being connected to the gate of the third load transistor and to one variable impedance terminal of the second load transistor, the other variable impedance terminal of the second load transistor being connected to a variable impeDance terminal of the third load transistor.

Claim 4

An amplifying circuit as in claim 1 wherein the high dynamic impedance load further includes three transistors connected in series, with the impedance of each transistor controlled by a base, the base of each transistor being connected to a variable impedance terminal of one of the load field effect transistors.

Claim 5

An amplifying circuit as in claim 1 wherein said high impedance load has a high impedance load output terminal and a low impedance load output terminal and the output is taken from the high impedance load output terminal.

Claim 6

An amplifying circuit as in claim 1 wherein the said high dynamic impedance load consists of at least two load field effect transistors with the gate of the first load transistor being connected to said third terminal and a variable impedance terminal of said first load transistor being connected to the gate of the second transistor.

Claim 7

The circuit of claim 5 wherein an adjustable resistor is connected between said third terminal and said variable impedance terminal of said first load transistor.

Claim 8

The circuit of claim 5 wherein the field effect transistors are metal-oxide-semiconductors.

Claim 9

A circuit providing a high dynamic impedance load and including an input terminal, a resistor having first and second terminals with its first terminal connected to said input terminal, at least three field effect transistors each having a control gate to vary the impedance across its two other variable impedance terminals, the gate of the first field effect transistor being connected to said input terminal, a variable impedance terminal of said first transistor being connected to said second resistor terminal and to the gate of said second transistor, the other variable impedance terminal of the first transistor being connected to the gate of the third transistor and to one variable impedance terminal of the second transistor, the other variable impedance terminal of the second transistor being connected to a variable impedance terminal of the third transistor, wherein the pinch-off voltage of said third transistor is higher than the pinch-off voltage of said second transistor and the pinch-off voltage of said second transistor is higher than the pinch-off voltage of said first transistor.

Claim 10

A circuit providing a high dynamic impedance load and including an input terminal, a resistor having first and second terminals with its first terminal connected to said input terminal, at least three field effect transistors each having a control gate to vary the impedance across its two other variable impedance terminals, the gate of the first field effect transistor being connected to said input terminal, a variable impedance terminal of said first transistor being connected to said second resistor terminal and to the gate of said second transistor, the other variable impedance terminal of the first transistor being connected to the gate of the third transistor and to one variable impedance terminal of the second transistor, the other variable impedance terminal of the second transistor being connected to a variable impedance terminal of the third transistor, wherein the pinch-off voltage of said third transistor is higher than the pinch-off voltage of said second transistor and the pinch-off voltage of said second transistor is higher than the pinch-off voltage of said first transistor.

Claim 11

A circuit providing a high dynamic impedance load and including an input terminal, a first resistor having first and second terminals with its first terminal connected to said input terminal,at least three field effect transistors each having a control gate to vary the impedance across its two other variable impedance terminals, second and third resistors connected in series and each having first and second terminals, the gate of the first field effect transistor being connected to said input terminal, a variable impedance terminal of said first transistor being connected to said second resistor terminal, the other variable impedance terminal of the first transistor being connected to one variable impedance terminal of the second transistor, the other variable impedance terminal of the second transistor being connected to a variable impedance terminal of the third transistor; wherein the gate of the first transistor is connected to the first terminal of the second resistor, the gate of the second transistor is connected to the second terminal of the second resistor and to the first terminal of the third resistor and the gate of the third transistor is connected to the second terminal of the third resistor.

Claim 12

A circuit providing a high dynamic impedance load and including an input terminal, a first resistor having first and second terminals with its first terminal connected to said input terminal,at least three field effect transistors each having a control gate to vary the impedance across its two other variable impedance terminals, second and third resistors connected in series and each having first and second terminals, the gate of the first field effect transistor being connected to said input terminal, a variable impedance terminal of said first transistor being connected to said second resistor terminal, the other variable impedance terminal of the first transistor being connected to one variable impedance terminal of the second transistor, the other variable impedance terminal of the second transistor being connected to a variable impedance terminal of the third transistor; wherein the gate of the first transistor is connected to the first terminal of the second resistor, the gate of the second transistor is connected to the second terminal of the second resistor and to the first terminal of the third resistor and the gate of the third transistor is connected to the second terminal of the third resistor.