Dynamic random access memory

Claim 1

A process for making a random access memory in which a plurality of memory cells are arranged in rows and columns and each memory cell includes a transistor and a capacitor with one plate of the capacitor being merged with a virtual drain zone of the transistor, which includes the steps of preparing a silicon chip which includes active portions where memory cells are to be formed and passive portions which serve to isolate the active portions CHARACTERIZED IN THAT the process includes the steps of depositing over the silicon chip and insulated therefrom a first polycrystalline silicon layer which is patterned to provide a storage electrode over at least that region of each active portion which serves as the merged plate of the capacitor of a cell, depositing over the chip a second polycrystalline silicon layer which is electrically insulated from the patterned electrodes of the first layer and which is thereafter suitably patterned to form both a plurality of gate electrodes, one over at least the region of each active portion which is to serve as the channel of the transistor of a cell, and a plurality of conductive lines each of which has a portion which directly contacts the silicon chip at a part of the active portion which is to serve as the source of the transistor, wherein each conductive line connects all of the transistors common to a separate column of the array, converting the conductivity type of each active portion which is to serve as a source of a transistor, both in the region between the gate electrode and the directly contacting portion of the conductive line and in a region underlying the directly contacting portion, and forming over the chip and insulated therefrom a second plurality of lines, each line of said second plurality electrically contacting the gate electrodes of all the transistors common to a separate row of the array.