US4239990A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock voltage generator for semiconductor memory with reduced power dissipation
Assignee: Texas Instruments Inc
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Filing: 1978-09-07
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Granted: 1980-12-16
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Expires: 1998-09-07
Abstract
Abstract A clock generator for producing internal waveforms for an MOS dynamic RAM or the like provides a preselected delay period between input and output clocks. A pair-delay circuit including two transistor stages produces the desired delay, a driver circuit provides the necessary high level output. A pair of series transistors in the output of the pair-delay, with the node between the series transistors being precharged, provides precise control of the delay over a wide range. Power dissipation is reduced in the driver circuit by avoiding the possibility of d.c. current paths when the reset clock goes high.
Inventors
- 👤 Ngai H. Hong
- 👤 Edmund A. Reese
- 👤 Donald J. Redwine
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:53
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/4063; G11C11/407; G11C11/4076; G11C11/409; G11C11/4093; H10; H10B; H10B12/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
170 words
A clock generator circuit comprising: an input terminal for receiving a reference clock voltage; a delay circuit connected to the input terminal and producing a delayed intermediate voltage at an output; a driver circuit having an input connected to receive said output and producing a high level delayed clock voltage at an output terminal; the improvement wherein the driver circuit includes in addition a pair of controlled switching devices each having a current path and a control element, the current path of one of the pair of switching devices being connected between said output terminal and a high voltage node, the current path of the other of the pair of switching devices being connected between said high voltage node and a reference potential, the control elements of the pair of switching devices being connected together and to a reset clock voltage occurring after said delayed intermediate voltage, whereby said output terminal and said high voltage node are both discharged for reset without establishing a direct current path to reference potential.
Claim 2
Dependent Claim
170 words
A clock generator circuit comprising: an input terminal for receiving a reference clock voltage; a delay circuit connected to the input terminal and producing a delayed intermediate voltage at an output; a driver circuit having an input connected to receive said output and producing a high level delayed clock voltage at an output terminal; the improvement wherein the driver circuit includes in addition a pair of controlled switching devices each having a current path and a control element, the current path of one of the pair of switching devices being connected between said output terminal and a high voltage node, the current path of the other of the pair of switching devices being connected between said high voltage node and a reference potential, the control elements of the pair of switching devices being connected together and to a reset clock voltage occurring after said delayed intermediate voltage, whereby said output terminal and said high voltage node are both discharged for reset without establishing a direct current path to reference potential.
Claim 3
Dependent Claim
30 words
A circuit according to claim 1 wherein the pair of switching devices are insulated gate field effect transistors, the current paths are source-to-drain paths, and the control elements are gates.
Claim 4
Dependent Claim
37 words
A circuit according to claim 2 wherein the driver circuit includes in addition another switching device having a current path connecting the output terminal to reference potential and a control element connected to receive the delayed voltage.
Claim 5
Dependent Claim
46 words
A circuit according to claim 3 wherein said one of said pair of switching devices which has its current path connected between said high voltage node and reference potential is ion-implanted to provide a higher threshold voltage than said other of said pair of switching devices.
Claim 6
Dependent Claim
40 words
A circuit according to claim 2 wherein the driver circuit includes in addition a third switching device having a source-to-drain path connected between a voltage supply and said output terminal and having a gate connected to said high voltage node.
Claim 7
Dependent Claim
25 words
A circuit according to claim 5 wherein means are provided for charging said high voltage node at a time prior to said delayed clock voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-12-16 | 1984-06-16 | 1984-12-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-12-16 | 1988-06-16 | 1988-12-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-12-16 | 1992-06-16 | 1992-12-16 | $7700.00 | Window Closed / Lapsed |