US4238838A
Expired / Lapsed
US
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Core memory wiring arrangement
Assignee: Ampex Corp
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Filing: 1978-05-16
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Granted: 1980-12-09
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Expires: 1998-05-16
Abstract
Abstract A large, 2 wire, 2-1/2D core memory includes four, 1K (1024) by 1280, core frames with 1280 Y conductors each stringing and inductively coupling a column of 1024 cores in each of the four frames and 4K orthogonal X conductors each stringing and inductively coupling one row of 1280 cores. A word position within the memory is defined by 5 pairs of Y conductors, a corresponding X conductor from each frame, and selection of relative current directions in the Y conductors. Reading of a 20 bit word is accomplished with 5 sense amplifiers in four rapid succession read sub-operations. Digit sense conductor noise recovery time is minimized by arranging for balanced, predictable delta noise on each digit sense conductor of a pair and by providing a multiple digit sense conductor pair crossover arrangement which results in a balancing of image current coupling into adjacent digit sense conductor pairs.
Inventors
- 👤 Kurt Wright
- 👤 Thomas J. Gilligan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:06
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/02; G11C11/06; G11C11/06007; G11C11/06014; G11C11/06021; G11C11/06028; G11C11/06035; G11C5/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
203 words
A two wire core memory comprising: at least two arrays of magnetic memory cores which are switchable between different states of magnetization; a plurality of word conductors for each array, each word conductor inductively coupling a plurality of cores in an array; at least two groups of digit-sense conductors inductively coupling a plurality of cores from each array, each group including two subgroups of at least one digit-sense conductor each with digit-sense conductors which occupy corresponding physical positions in each subgroup of a group forming a digit-sense conductor pair, the subgroups of each group occupying a first relative position within one array and being crossed over one another between the same two arrays to occupy a relative position opposite the first relative position in a second array different from the one array, the at least one digit-sense conductor within each subgroup occupying the same relative physical positions in the subgroup in both the first and second arrays; and control circuitry that is operative during a memory cycle to provide coincident selection by passing a current through a word conductor and a balanced pair of currents through a pair of digit-sense conductors tending to switch at least one selected core in the memory. PG,41
Claim 2
Dependent Claim
203 words
A two wire core memory comprising: at least two arrays of magnetic memory cores which are switchable between different states of magnetization; a plurality of word conductors for each array, each word conductor inductively coupling a plurality of cores in an array; at least two groups of digit-sense conductors inductively coupling a plurality of cores from each array, each group including two subgroups of at least one digit-sense conductor each with digit-sense conductors which occupy corresponding physical positions in each subgroup of a group forming a digit-sense conductor pair, the subgroups of each group occupying a first relative position within one array and being crossed over one another between the same two arrays to occupy a relative position opposite the first relative position in a second array different from the one array, the at least one digit-sense conductor within each subgroup occupying the same relative physical positions in the subgroup in both the first and second arrays; and control circuitry that is operative during a memory cycle to provide coincident selection by passing a current through a word conductor and a balanced pair of currents through a pair of digit-sense conductors tending to switch at least one selected core in the memory. PG,41
Claim 3
Dependent Claim
41 words
The core memory according to claim 1 above, further comprising a sense amplifier that is coupled for operation during a read portion of a memory cycle to sense a core switching signal differentially across a pair of current carrying digit-sense conductors.
Claim 4
Dependent Claim
74 words
The core memory according to claim 1 above, wherein the memory is a two wire 21/2 D memory having each core coupled by a unique combination of one word conductor and one digit-sense conductor with the core orientations selected such that a given one of a pair of cores coupled by one word conductor and a pair of digit-sense conductors may be selected by the relative current directions in the word and digit-sense conductors.
Claim 5
Dependent Claim
68 words
The core memory according to claim 3 above, wherein the control circuitry is operative during a memory cycle to sequentially select one core each from the first and second arrays which inductively couples a given digit-sense conductor, the selected cores being partially selected by word conductor currents in the first and second arrays which have opposite polarities relative to the currents in the given pair of digit-sense conductors.
Claim 6
Dependent Claim
49 words
The core memory according to claim 3 above, wherein the control circuitry is operative during a memory cycle to sequentially select one core each from the first and second arrays, the selected cores in the first and second arrays inductively coupling different conductors of a given digit-sense conductor pair.
Claim 7
Dependent Claim
36 words
The core memory according to claim 5 above, wherein the control circuitry includes circuitry operative during a memory cycle to first read sequentially and then write sequentially the selected cores in the first and second arrays.
Claim 8
Dependent Claim
55 words
The core memory according to claim 1 above, wherein the memory comprises first through fourth arrays disposed sequentially along the digit-sense conductors, the subgroups of each group of digit-sense conductors being crossed over between the first and second arrays and between the third and fourth arrays with no crossover between the second and third arrays.
Claim 9
Dependent Claim
146 words
A two wire, one core per bit core memory comprising pairs of arrays of magnetic memory cores; a plurality of word conductors for each array, each word conductor inductively coupling a plurality of cores in an array and a plurality of digit-sense conductors coupled to carry partial selection currents in parallel equal magnitude pairs during each read and each write portion of each memory cycle, all of the digit-sense conductors being disposed in subgroup pairs arranged to provide current carrying conductor pairs in respective corresponding relative positions in the subgroups with all of the subgroup pairs having first and opposite juxtapositions in first and opposite arrays respectively of a pair of arrays to achieve noise cancellation with the two conductors of each nonselected digit-sense conductor pair having equal and balanced electrical noise signals coupled thereto from a pair of digit-sense conductors selected during a memory cycle.
Claim 10
Dependent Claim
146 words
A two wire, one core per bit core memory comprising pairs of arrays of magnetic memory cores; a plurality of word conductors for each array, each word conductor inductively coupling a plurality of cores in an array and a plurality of digit-sense conductors coupled to carry partial selection currents in parallel equal magnitude pairs during each read and each write portion of each memory cycle, all of the digit-sense conductors being disposed in subgroup pairs arranged to provide current carrying conductor pairs in respective corresponding relative positions in the subgroups with all of the subgroup pairs having first and opposite juxtapositions in first and opposite arrays respectively of a pair of arrays to achieve noise cancellation with the two conductors of each nonselected digit-sense conductor pair having equal and balanced electrical noise signals coupled thereto from a pair of digit-sense conductors selected during a memory cycle.
References Cited (Backward Citations)
US3305846A
Cited
US3864672A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-12-09 | 1984-06-09 | 1984-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-12-09 | 1988-06-09 | 1988-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-12-09 | 1992-06-09 | 1992-12-09 | $7700.00 | Window Closed / Lapsed |