Memory with improved arrangement of conductors linking memory elements to reduce disturbances

Claim 1

A MEMORY COMPRISING AN EVEN PLURALITY OF MEMORY PLANES ARRANGED IN A STACK AND EACH HAVING A TOP SIDE AND A BOTTOM SIDE, EACH SIDE INCLUDING AN ARRAY OF PAIRS OF MEMORY ELEMENTS ARRANGED IN DIGIT PAIR ROWS AND WORD COLUMNS, DIGIT CONDUCTOR PAIRS LINKING PAIRS OF MEMORY ELEMENTS ALONG CORRESPONDING ROWS ON THE TOP SIDES OF ALL PLANES, AND DIGIT CONDUCTOR PAIRS LINKING PAIRS OF MEMORY ELEMENTS ALONG CORRESPONDING ROWS ON THE BOTTOM SIDES OF ALL PLANES, THE CONDUCTORS OF THE DIGIT CONDUCTOR PAIRS OF EACH OF THE TOP AND BOTTOM SIDES OF ALL PLANES EXTENDING BETWEEN PLANES WITH ALTERNATING STAGGERED STRAIGHT PATHS AND CROSSED PATHS, THE DIGIT CONDUCTOR PAIRS ON THE TOP SIDES OF ALL PLANES EXTENDING BETWEEN PLANES ON ALTERNATING SIDES OF THE STACK SO THAT THE CONDUCTOR PAIRS FOLLOW RECTANGULAR ZIGZAG PATHS, THE DIGIT CONDUCTOR PAIRS ON THE BOTTOM SIDES OF ALL PLANES EXTENDING BETWEEN PLANES ON DIFFERENT ALTERNATING SIDES OF THE STACK SO THAT THE CONDUCTOR PAIRS FOLLOW COMPLEMENTARY RECTANGULAR PATHS, IMPEDANCE TERMINATIONS CONNECTED AT BOTH ENDS OF ALL DIGIT CONDUCTORS, THE DIGIT CONDUCTORS ON THE TOP SIDES OF THE PLANES HAVING TERMINATIONS ON A FIRST SIDE OF THE STACK AND DIGIT CONDUCTORS ON THE BOTTOM SIDES OF THE PLANES HAVING TERMINATIONS ON THE OPPOSITE SECOND SIDE OF THE STACK, AND DIGIT DRIVERS AND DIFFERENTIAL SENSE AMPLIFIERS COUPLED ON SAID FIRST AND SECOND SIDES OF THE STACK TO THE MIDPOINTS OF RESPECTIVE DIGIT CONDUCTOR PAIRS.