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US4238740A Expired / Lapsed US ⏱️ 0.0 years remaining

Phase-locked loop for PCM transmission systems

Assignee: AT&T Inc
•
Filing: 1979-02-02
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Granted: 1980-12-09
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Expires: 1999-02-02
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Abstract

Abstract A phase-locked loop for PCM transmission systems has a phase comparator (20) which provides continuous regulation of the loop oscillator (30). When a PCM pulse signal is present, the phase comparator selectively compares the PCM and oscillator clock signal and generates an error signal which synchronizes the oscillator to the PCM frequency. During the absence of a PCM pulse, the phase comparator provides a high impedance output and oscillator synchronization is maintained by a loop filter (23). In the disclosed embodiment, the phase comparator is a dual section tristate gate (300).

Inventors

  • 👤 Charles R. Crue

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 04:39
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H04; H04L; H04L7/00; H04L7/02; H04L7/027

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 195 words
A phase-locked loop circuit for extracting a clock signal from a PCM signal comprising a voltage controlled oscillator (30) connected in a phase-locked loop for generating a clock signal having a frequency determined by a control signal (14) produced within the phase-locked loop, characterized in that said loop circuit further includes phase comparison means (20) for selectively comparing the phase between a PCM signal and the oscillator clock signal only at times when a PCM pulse is present and generating therefrom a control signal to synchronize the oscillator clock at the PCM frequency, said means providing a high impedance output at times when a PCM pulse is absent, said means comprising a dual section tri-state gate (300) including voltage means (303) for providing the voltage required to cause said voltage controlled oscillator to oscillate at a predetermined frequency, and filter means (23) connected between the output of said phase comparison means and the input (28, 29) of said voltage controlled oscillator for coupling said control signal to said oscillator, the output (26, 27) of said filter means further serving to hold the oscillator frequency fixed during the high impedance state of said phase comparison means.
Claim 2
Dependent Claim 195 words
A phase-locked loop circuit for extracting a clock signal from a PCM signal comprising a voltage controlled oscillator (30) connected in a phase-locked loop for generating a clock signal having a frequency determined by a control signal (14) produced within the phase-locked loop, characterized in that said loop circuit further includes phase comparison means (20) for selectively comparing the phase between a PCM signal and the oscillator clock signal only at times when a PCM pulse is present and generating therefrom a control signal to synchronize the oscillator clock at the PCM frequency, said means providing a high impedance output at times when a PCM pulse is absent, said means comprising a dual section tri-state gate (300) including voltage means (303) for providing the voltage required to cause said voltage controlled oscillator to oscillate at a predetermined frequency, and filter means (23) connected between the output of said phase comparison means and the input (28, 29) of said voltage controlled oscillator for coupling said control signal to said oscillator, the output (26, 27) of said filter means further serving to hold the oscillator frequency fixed during the high impedance state of said phase comparison means.
Claim 3
Dependent Claim 19 words
The phase-locked loop circuit of claim 1 wherein said filter means (23) comprises a balanced lag-lead RC type filter.
Claim 4
Dependent Claim 19 words
The phase-locked loop circuit of claim 2 wherein said voltage controlled oscillator (30) comprises a stable RC type multivibrator.

References Cited (Backward Citations)

US3351868A Cited
US3701039A Cited
US3983506A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1983-12-09 1984-06-09 1984-12-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1987-12-09 1988-06-09 1988-12-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1991-12-09 1992-06-09 1992-12-09 $7700.00 Window Closed / Lapsed

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