Power control system

Claim 2

A power control system comprising: first means including at least one SCR solid state switch device connected with its main current carrying path in series between a source of AC power and a load; second means for generating an SCR gate signal for firing of said SCR, said gate signal occurring in synchronism only during one half cycle of said AC power source having a duration which is variable in response to a characteristic of an externally generated control signal; and third means with said second means for generating a series of signal ramp waves, said ramp waves each being synchronous with a corresponding AC power half cycle, said third means generating said signal ramp as a substantially linear voltage ramp and said value of said externally generated control signal is its voltage at said time of crossing, said third means further comprising means for generating a substantially square wave signal corresponding to one of the positive and negative half waves of said AC source, a capacitor charge circuit also including a solid state device exhibiting a substantially initial constant current characteristic, said circuit providing said square wave signals through said solid state device for substantially constant current charging of said capacitor during each of said square waves to provide said linear voltage ramp and means for providing a pedestal amplitude for said linear voltage ramp; fourth means within said second means comprising a comparator for generating a series of said SCR gate signals when the instantaneous value of said signal ramp crosses over the value of said externally generated control signal at the time of said crossing; and fifth means for applying said SCR gate signals to said SCR switch device to control the fraction of each AC cycle which causes current to flow in said SCR main current carrying path.

Claim 3

Apparatus according to claim 1 in which said fifth means comprises a power amplifier.

Claim 4

Apparatus according to claim 1 in which said solid state device is a NAND gate of the CMOS type.

Claim 5

An AC power controller for providing full wave power control in response to an externally generated control signal and in which at least one pair of SCR solid state switching elements is connected with anode-cathode main current carrying paths in parallel in reverse polarities between a source of AC power and a load, comprising: first means connected to said AC source for driving first and second trains of signals of the same polarity, said first train of signals being synchronous with the positive half cycles of said AC source and said second source and said second train of signals being synchronous with said negative half-cycle of said AC source, a full-wave diode bridge connected to said AC source at first and second opposite terminals thereof and providing signals from said terminals thereof, which are said first and second signal trains of the same polarity; second means comprising a pair of squaring circuits each responsive to one of said trains of signals to produce corresponding first and second substantially square wave signal trains; third means responsive to said second means for producing first and second trains of signal ramps each synchronous and contemporaneous with a corresponding one of said square wave signal trains comprising separate first and second voltage ramp generators responsive to said first and second square wave trains from said second means, respectively, said ramp generators each comprising a capacitor and a solid state device having a substantially constant circuit characteristic, said capacitor being connected in a charge circuit for producing said signal ramps as substantially linear voltage ramps beginning with the leading edge of the individual square waves of said square wave trains and extending at least to the trailing edge of each of said square waves and means for providing a pedestal amplitude for said signal ramps; fourth means for continuously comparing said first and second trains of signal ramps to the amplitude of said externally generated control signal to produce separate first and second SCR gates beginning substantially at the time of cross-over of the instantaneous amplitude of each of the corresponding ramps and said externally generated control signal, said SCR gates thereby varying in duration as a function of said externally generated control signal amplitude; and fifth means for applying said sequence SCR gates each to a corresponding one of said SCR devices to provide said full wave control of the power passing through said SCR main current carrying paths.

Claim 6

An AC power controller for providing full wave power control in response to an externally generated control signal and in which at least one pair of SCR solid state switching elements is connected with anode-cathode main current carrying paths in parallel in reverse polarities between a source of AC power and a load, comprising: first means connected to said AC source for driving first and second trains of signals of the same polarity, said first train of signals being synchronous with the positive half cycles of said AC source and said second source and said second train of signals being synchronous with said negative half-cycle of said AC source, a full-wave diode bridge connected to said AC source at first and second opposite terminals thereof and providing signals from said terminals thereof, which are said first and second signal trains of the same polarity; second means comprising a pair of squaring circuits each responsive to one of said trains of signals to produce corresponding first and second substantially square wave signal trains; third means responsive to said second means for producing first and second trains of signal ramps each synchronous and contemporaneous with a corresponding one of said square wave signal trains comprising separate first and second voltage ramp generators responsive to said first and second square wave trains from said second means, respectively, said ramp generators each comprising a capacitor and a solid state device having a substantially constant circuit characteristic, said capacitor being connected in a charge circuit for producing said signal ramps as substantially linear voltage ramps beginning with the leading edge of the individual square waves of said square wave trains and extending at least to the trailing edge of each of said square waves and means for providing a pedestal amplitude for said signal ramps; fourth means for continuously comparing said first and second trains of signal ramps to the amplitude of said externally generated control signal to produce separate first and second SCR gates beginning substantially at the time of cross-over of the instantaneous amplitude of each of the corresponding ramps and said externally generated control signal, said SCR gates thereby varying in duration as a function of said externally generated control signal amplitude; and fifth means for applying said sequence SCR gates each to a corresponding one of said SCR devices to provide said full wave control of the power passing through said SCR main current carrying paths.

Claim 7

Apparatus according to claim 4 in which said fourth means comprises first and second differential amplifiers having first and second input terminals responsive to said first and second trains of signal ramps from said third means, respectively, at their corresponding first terminals and to said externally generated control signal, said externally generated control signal having a range of values substantially the same as the range of instantaneous values of said ramp signals, and in which said fourth means also comprises means responsive to said first and second differential amplifier outputs to initiate the corresponding ones of said SCR gate signals substantially at the times of instantaneous equality of said externally generated control signal and the corresponding ramp signal.

Claim 8

Apparatus according to claim 4 in which said fifth means comprises first and second power amplifiers responsive to said first and second SCR gates generated by said fourth means.

Claim 9

Apparatus according to claim 4 in which said fifth means comprises an electric signal-to-light transducer responsive to each of said SCR gates, a light-to-electric signal transducer and optical means coupling said transducers to produce said SCR gates in isolated form, whereby the circuits of said fifth means may be electrically isolated from said fourth means to accommodate high load and source voltages.

Claim 10

Apparatus according to claim 4 in which electrically isolating means are included for coupling said fourth and fifth means to isolate said first, second and third and fourth means may be isolated from said load and source voltages extant at said SCR's.

Claim 11

Apparatus according to claim 4 in which said fifth means comprises means for providing a firing spike on the leading edge of each of said SCR gates.

Claim 12

An AC power controller for providing full wave power control in response to an externally generated control signal and in which at least one pair of SCR solid state switching elements is connected with anode-cathode main current carrying paths in parallel in reverse polarities between a source of AC power and a load, comprising: first means connected to said AC source for driving first and second trains of signals of the same polarity, said first train of signals being synchronous with the positive half cycles of said AC source and said second source and said second train of signals being synchronous with said negative half-cycle of said AC source, a full-wave diode bridge connected to said AC source at first and second opposite terminals thereof and providing signals from said terminals thereof, which are said first and second signal trains of the same polarity; second means comprising a pair of squaring circuits each responsive to one of said trains of signals to produce corresponding first and second substantially square wave signal trains and further comprising a separate amplifier responsive to each of said first means trains, said amplifier providing sufficient gain to steepen the rise and fall times of the waves of said trains and being adapted to saturate for flattening said signal tops to produce said corresponding first and second square wave signal trains; third means responsive to said second means for producing first and second trains of signal ramps each synchronous and contemporaneous with a corresponding one of said square wave signal trains comprising separate first and second voltage ramp generators responsive to said first and second square wave trains from said second means, respectively, said ramp generators each comprising a capacitor and a solid state device having a substantially constant current characteristic, said capacitor being connected in a charge circuit for producing said signal ramps as substantially linear voltage ramps beginning with the leading edge of the individual square waves of said square wave trains and extending at least to the trailing edge of each of said square waves and means for providing a pedestal amplitude for said ramps; fourth means for continuously comparing said first and second trains of signal ramps to the amplitude of said externally generated control signal to produce separate first and second SCR gates beginning substantially at the time of cross-over of the instantaneous amplitude of each of the corresponding ramps and said externally generated control signal, said SCR gates thereby varying in duration as a function of said externally generated control signal amplitude; and fifth means for applying said separate SCR gates each to a corresponding one of said SCR devices to provide said full wave control of the power passing through said SCR main current carrying paths.

Claim 13

An AC power controller for providing full wave power control in response to an externally generated control signal and in which at least one pair of SCR solid state switching elements is connected with anode-cathode main current carrying paths in parallel in reverse polarities between a source of AC power and a load, comprising: first means connected to said AC source for driving first and second trains of signals of the same polarity, said first train of signals being synchronous with the positive half cycles of said AC source and said second source and said second train of signals being synchronous with said negative half-cycle of said AC source, a full-wave diode bridge connected to said AC source at first and second opposite terminals thereof and providing signals from said terminals thereof, which are said first and second signal trains of the same polarity; second means comprising a pair of squaring circuits each responsive to one of said trains of signals to produce corresponding first and second substantially square wave signal trains and further comprising a separate amplifier responsive to each of said first means trains, said amplifier providing sufficient gain to steepen the rise and fall times of the waves of said trains and being adapted to saturate for flattening said signal tops to produce said corresponding first and second square wave signal trains; third means responsive to said second means for producing first and second trains of signal ramps each synchronous and contemporaneous with a corresponding one of said square wave signal trains comprising separate first and second voltage ramp generators responsive to said first and second square wave trains from said second means, respectively, said ramp generators each comprising a capacitor and a solid state device having a substantially constant current characteristic, said capacitor being connected in a charge circuit for producing said signal ramps as substantially linear voltage ramps beginning with the leading edge of the individual square waves of said square wave trains and extending at least to the trailing edge of each of said square waves and means for providing a pedestal amplitude for said ramps; fourth means for continuously comparing said first and second trains of signal ramps to the amplitude of said externally generated control signal to produce separate first and second SCR gates beginning substantially at the time of cross-over of the instantaneous amplitude of each of the corresponding ramps and said externally generated control signal, said SCR gates thereby varying in duration as a function of said externally generated control signal amplitude; and fifth means for applying said separate SCR gates each to a corresponding one of said SCR devices to provide said full wave control of the power passing through said SCR main current carrying paths.

Claim 14

Apparatus according to claim 10 in which said fourth means comprises first and second differential amplifiers having first and second input terminals responsive to said first and second trains of signal ramps from said third means, respectively, at their corresponding first terminals and to said externally generated control signal, said externally generated control signal having a range of values substantially the same as the range of instantaneous values of said ramp signals, and in which said fourth means also comprises means responsive to said first and second differential amplifier outputs to initiate the corresponding ones of said SCR gate signals substantially at the times of instantaneous equality of said externally generated control signal and the corresponding ramp signal.

Claim 15

Apparatus according to claim 11 in which said fifth means comprises first and second power amplifiers responsive to said first and second SCR gates generated by said fourth means.

Claim 16

Apparatus according to claim 12 in which said fifth means comprises an electric signal-to-light transducer responsive to each of said SCR gates, a light-to-electric signal transducer and optical means coupling said transducers to produce said SCR gates in isolated form, whereby the circuits of said fifth means may be electrically isolated from said fourth means to accommodate high load and source voltages.

Claim 17

Apparatus according to claim 13 in which said electric-to-light transducers are light emitting diodes, said light-to-electric transducers are photo transistors, and said means optically coupling said transducers is an electrically insulating but light conducting medium.

Claim 18

Apparatus according to claim 14 in which said fifth means comprises means for providing an immediate firing spike and subsequent holding current on the leading edge of said SCR gates comprising a normally non-conductive photo-transistor and a normally non-conductive output switch, said normally non-conductive output switch being conductive immediately open conduction of said normally non-conductive photo-transistor.

Claim 19

A ramp generator for producing an output sawtooth signal in response to a square wave pulse input signal comprising: a first and second NAND gate each having a first and second input terminal and an output terminal; means for coupling the input square wave pulse to the input terminals of said first NAND gate; means for coupling the first NAND gate output terminal to said second NAND gate first input terminal; a charging capacitor coupled between said second NAND gate output terminal and said second NAND gate second input terminal, and a slope control resistor coupled between said first NAND gate output terminal and said second NAND gate second input terminal for controlling the slope of said output sawtooth signal generated at said second NAND gate output terminal and a resistor connected in series with said charging capacitor for controlling the initial ramp amplitude of said sawtooth signal.

Claim 20

A ramp generator for producing an output sawtooth signal in response to a square wave pulse input signal comprising: a first and second NAND gate each having a first and second input terminal and an output terminal; means for coupling the input square wave pulse to the input terminals of said first NAND gate; means for coupling the first NAND gate output terminal to said second NAND gate first input terminal; a charging capacitor coupled between said second NAND gate output terminal and said second NAND gate second input terminal, and a slope control resistor coupled between said first NAND gate output terminal and said second NAND gate second input terminal for controlling the slope of said output sawtooth signal generated at said second NAND gate output terminal and a resistor connected in series with said charging capacitor for controlling the initial ramp amplitude of said sawtooth signal.

Claim 21

A ramp generator in accordance with claim 16 wherein said NAND gate is of the C-MOS type having an inherent input constant current characteristic.

Claim 22

Circuit means for providing variable pulse width power frequency signals of the same polarity but of 180 degree relative phase from a full-wave input signal comprising; a diode bridge formed of two pairs of series connected diodes; means for coupling said full-wave input signal across the junction of each pair of said series connected diodes; means for coupling one of said power frequency signals from each of said junctions; and means for adjusting said power frequency signal pulse width while retaining said relative phase comprising a biasing network coupled to said junctions.

Claim 23

Circuit means for providing variable pulse width power frequency signals of the same polarity but of 180 degree relative phase from a full-wave input signal comprising; a diode bridge formed of two pairs of series connected diodes; means for coupling said full-wave input signal across the junction of each pair of said series connected diodes; means for coupling one of said power frequency signals from each of said junctions; and means for adjusting said power frequency signal pulse width while retaining said relative phase comprising a biasing network coupled to said junctions.

Claim 24

An AC power controller for providing full wave power control in response to an externally generated control signal and in which at least one pair of SCR solid state switching elements is connected with anode-cathode main current carrying paths in parallel in reverse polarities between a source of AC power and a load, comprising: first means connected to said AC source for driving first and second trains of signals of the same polarity, said first train of signals being synchronous with the positive half cycles of said AC source and said second source and said second train of signals being synchronous with said negative half-cycle of said AC source, a full-wave diode bridge connected to said AC source at first and second opposite terminals thereof and providing signals from said terminals thereof, which are said first and second signal trains of the same polarity, said full-wave diode bridge including a resistor tap network for providing signals at said AC source first and second opposite terminals whose pulse width vary from 180° retaining the relative phase; second means comprising a pair of squaring circuits each responsive to one of said trains of signals to produce corresponding first and second substantially square wave signal trains; third means responsive to said second means for producing first and second trains of signal ramps each synchronous and contemporaneous with a corresponding one of said square wave signal trains; fourth means for continuously comparing said first and second trains of signal ramps to the amplitude of said externally generated control signal to produce separate first and second SCR gates beginning substantially at the time of cross-over of the instantaneous amplitude of each of the corresponding ramps and said externally generated control signal, said SCR gates thereby varying in duration as a function of said externally generated control signal amplitude; and fifth means for applying said separate SCR gates each to a corresponding one of said SCR devices to provide said full wave control of the power passing through said SCR main current carrying paths.

Claim 25

An AC power controller for providing full wave power control in response to an externally generated control signal and in which at least one pair of SCR solid state switching elements is connected with anode-cathode main current carrying paths in parallel in reverse polarities between a source of AC power and a load, comprising: first means connected to said AC source for driving first and second trains of signals of the same polarity, said first train of signals being synchronous with the positive half cycles of said AC source and said second source and said second train of signals being synchronous with said negative half-cycle of said AC source, a full-wave diode bridge connected to said AC source at first and second opposite terminals thereof and providing signals from said terminals thereof, which are said first and second signal trains of the same polarity, said full-wave diode bridge including a resistor tap network for providing signals at said AC source first and second opposite terminals whose pulse width vary from 180° retaining the relative phase; second means comprising a pair of squaring circuits each responsive to one of said trains of signals to produce corresponding first and second substantially square wave signal trains; third means responsive to said second means for producing first and second trains of signal ramps each synchronous and contemporaneous with a corresponding one of said square wave signal trains; fourth means for continuously comparing said first and second trains of signal ramps to the amplitude of said externally generated control signal to produce separate first and second SCR gates beginning substantially at the time of cross-over of the instantaneous amplitude of each of the corresponding ramps and said externally generated control signal, said SCR gates thereby varying in duration as a function of said externally generated control signal amplitude; and fifth means for applying said separate SCR gates each to a corresponding one of said SCR devices to provide said full wave control of the power passing through said SCR main current carrying paths.