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US4237495A
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Circuit for doubling the number of output bits of a photodiode array
Assignee: Xerox Corp
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Filing: 1979-03-15
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Granted: 1980-12-02
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Expires: 1999-03-15
Abstract
Abstract A circuit for converting a series of photoelectric element array voltage outputs into twice the number of binary bits is described. Each photodiode output voltage is compared against two reference voltages to produce a two bit code word signifying a low, medium or high photodiode output. This is then operated on by a circuit implementation of a logic equation to produce a two bit serial output. The result is the frequency doubling of a photodiode array output for greater fidelity during transmission and reproduction of the original image.
Inventors
- 👤 Akimitsu Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:58
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/40; H04N1/405; H04N1/4055; H04N1/4056; H04N1/4051
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
122 words
The method of producing two serial binary output bits from the output voltage of each of an array of photoelectric converting elements comprising the steps of: comparing each element voltage output to two reference voltage levels, and using the results of said comparing step and the previous output bit to produce two serial output bits, (a) the two bits being both 1's or both 0's if the element output voltage is above the higher reference, or below the lower reference, respectively, or (b) the two bits being a 1 and a 0, or a 0 and a 1, if the element output voltage is between the reference levels, and the last previously produced output bit was a 1 or a 0, respectively.
Claim 2
Independent Claim
122 words
The method of producing two serial binary output bits from the output voltage of each of an array of photoelectric converting elements comprising the steps of: comparing each element voltage output to two reference voltage levels, and using the results of said comparing step and the previous output bit to produce two serial output bits, (a) the two bits being both 1's or both 0's if the element output voltage is above the higher reference, or below the lower reference, respectively, or (b) the two bits being a 1 and a 0, or a 0 and a 1, if the element output voltage is between the reference levels, and the last previously produced output bit was a 1 or a 0, respectively.
Claim 3
Independent Claim
109 words
The method of doubling the number of output bits from an array of photoelectric converting elements comprising the steps of comparing each element voltage to two reference levels and producing the following binary values of Ei and Fi, therefrom, (a) Ei=Fi=0 if the element output voltage is below both reference levels, (b) Ei=Fi=1 if the element output voltage is above both reference levels, and (c) Ei=1, Fi=0 if the element output voltage is between the reference levels, and generating two output image signals, Gi/2 and Gi2+0.5, according to the equation Gi/2=Ei·Fi+Gi/2-0.5·Ei·Fi Gi/2+0.5=Ei·Fi+Gi/2-0.5·Ei·Fi where Gi/2 and Gi2+0.5 are two binary output signals, and Gi/2-0.5 is the previous binary output signal.
Claim 4
Independent Claim
109 words
The method of doubling the number of output bits from an array of photoelectric converting elements comprising the steps of comparing each element voltage to two reference levels and producing the following binary values of Ei and Fi, therefrom, (a) Ei=Fi=0 if the element output voltage is below both reference levels, (b) Ei=Fi=1 if the element output voltage is above both reference levels, and (c) Ei=1, Fi=0 if the element output voltage is between the reference levels, and generating two output image signals, Gi/2 and Gi2+0.5, according to the equation Gi/2=Ei·Fi+Gi/2-0.5·Ei·Fi Gi/2+0.5=Ei·Fi+Gi/2-0.5·Ei·Fi where Gi/2 and Gi2+0.5 are two binary output signals, and Gi/2-0.5 is the previous binary output signal.
Claim 5
Dependent Claim
117 words
Apparatus for producing two serial binary bits of information from the voltage output of each element in an array of photoelectric elements comprising: means for generating two reference voltages, means for comparing said element output voltage to said reference voltages, and means for generating two serial bits for each element output voltage, (a) the two bits being both 1's or both 0's if the element output voltage is above the higher reference, or below the lower reference, respectively, (b) the two bits being a 1 and a 0, or a 0 and a 1, if the element output voltage was between the reference levels and the last previously produced bit was a 1 or a 0, respectively.
Claim 6
Dependent Claim
117 words
Apparatus for producing two serial binary bits of information from the voltage output of each element in an array of photoelectric elements comprising: means for generating two reference voltages, means for comparing said element output voltage to said reference voltages, and means for generating two serial bits for each element output voltage, (a) the two bits being both 1's or both 0's if the element output voltage is above the higher reference, or below the lower reference, respectively, (b) the two bits being a 1 and a 0, or a 0 and a 1, if the element output voltage was between the reference levels and the last previously produced bit was a 1 or a 0, respectively.
Claim 7
Dependent Claim
43 words
The apparatus of claim 3, said means for comparing comprising, two comparators, each for comparing a reference voltage to the instant array element output voltage and two latches for the temporary storage of the binary output of said comparators resulting from said comparison.
Claim 8
Dependent Claim
81 words
The apparatus of claim 3 wherein said means for generating comprises a digital circuit which is defined by the logic equations Gi/2=Ei·Fi+Gi/2-0.5·Ei·Fi Gi/2+0.5=Ei·Fi+Gi/2-0.5·Ei·Fi where Ei=Fi=0 if the array element output voltage is below both reference voltage levels, Ei=Fi=1 if the array element output voltage is above both reference voltages, Ei=1 and Fi=0 if the array element output voltage is between the reference voltage levels, Gi/2 and Gi/2+0.5 are the two binary output bits, and Gi/2-0.5 is the previous binary output bit.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-12-02 | 1984-06-02 | 1984-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-12-02 | 1988-06-02 | 1988-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-12-02 | 1992-06-02 | 1992-12-02 | $7700.00 | Window Closed / Lapsed |