Blemish compensating system for a solid state image pick-up device

Claim 2

A blemish compensating system used for a solid state image pick-up device having a plurality of image pick-up elements which are arranged to store electric charges corresponding to an optical image formed on the light sensitive portions thereof and are sequentially energized by a driving circuit in response to an output signal from a control signal generating means to derive out the electric charges stored on the respective image pick-up elements, comprising: memory means for storing address data representing the position of a defective solid state image pick-up element or elements; delay means for delaying the output signal from said image pick-up device by a time required for electrical signals to be taken out of those image pick-up elements of the image pick-up device which are horizontally arranged in a series; comparing means for comparing the address data corresponding to the position of that image pick-up element which is energized by said driving circuit to produce an output signal with the address data read out from said memory means, in which, when both the data are coincident with each other as a result of the comparison, said comparing means produces an output signal; and switching means permitting the output signal of the solid state image pick-up device to pass therethrough in a first switching position, and responding to the output signal from said comparing means to be set to a second switching position, thereby permitting the output signal from the solid state image pick-up device to pass therethrough by way of said delay means.

Claim 3

A blemish compensating system according to claim 1, in which said memory means sequentially stores address data representing the position of defective solid state image pick-up elements and which further comprises address specifying means for sequentially specifying the address for said memory means in response to an output signal from said comparing means, thereby sequentially reading said address data out of said memory means.

Claim 4

A blemish compensating system according to claim 2, in which said address specifying means is formed of a counter for counting an output signal from said comparing means and supplying a count output signal as an address specifying signal to said memory means.

Claim 5

A blemish compensating system used for a solid state image pick-up device having a plurality of image pick-up elements which are arranged to store electric charges corresponding to an optical image formed on the light sensitive portions thereof and are sequentially energized by a driving circuit in response to an output signal from a control signal generating means to derive out the electric charges stored on the respective image pick-up element comprising: memory means for storing address data representing the position of a defective solid state image pick-up element or elements; delay means for delaying the output signal from said image pick-up device by the time differing from a time for taking electrical signals out of those image pick-up elements of the image pick-up device which are horizontally arranged in series by a time for taking an electric signal from a single image pick-up element; comparing means for comparing the address data corresponding to the position of that image pick-up element which is energized by said driving circuit to produce an output signal with the address data read out from said memory means, in which, when both the data are coincident with each other as a result of the comparison, said comparing means produces an output signal; and switching means permitting the output signal of the solid state image pick-up device to pass therethrough in a first switching position, and responding to the output signal from said comparing means to be set to a second switching position, thereby permitting the output signal from the solid state image pick-up device to pass therethrough by way of said delay means.

Claim 6

A blemish compensating system used for a solid state image pick-up device having a plurality of image pick-up elements which are arranged to store electric charges corresponding to an optical image formed on the light sensitive portions thereof and are sequentially energized by a driving circuit in response to an output signal from a control signal generating means to derive out the electric charges stored on the respective image pick-up element comprising: memory means for storing address data representing the position of a defective solid state image pick-up element or elements; delay means for delaying the output signal from said image pick-up device by the time differing from a time for taking electrical signals out of those image pick-up elements of the image pick-up device which are horizontally arranged in series by a time for taking an electric signal from a single image pick-up element; comparing means for comparing the address data corresponding to the position of that image pick-up element which is energized by said driving circuit to produce an output signal with the address data read out from said memory means, in which, when both the data are coincident with each other as a result of the comparison, said comparing means produces an output signal; and switching means permitting the output signal of the solid state image pick-up device to pass therethrough in a first switching position, and responding to the output signal from said comparing means to be set to a second switching position, thereby permitting the output signal from the solid state image pick-up device to pass therethrough by way of said delay means.

Claim 7

A blemish compensating system according to claim 4, in which said memory means sequentially stores address data representing the position of defective solid state image pick-up elements and which further comprises address specifying means for sequentially specifying the address for said memory means in response to an output signal from said comparing means, thereby sequentially reading said address data out of said memory means.

Claim 8

A blemish compensating system used for a solid state image pick-up device having a plurality of image pick-up elements which are arranged to store electric charges corresponding to an optical image formed on the light sensitive portions thereof and are sequentially energized by a driving circuit in response to an output signal from a control signal generating means to derive out the electric charges stored on the respective image pick-up elements, comprising: memory means for storing address data representing the position of a defective solid state image pick-up element or elements; delay means for delaying an output signal from said solid state image pick-up device; comparing means for comparing the address data corresponding to the position of that image pick-up element which is energized by said driving circuit to produce an output signal with the address data read out from said memory means, in which, when both the data are coincident with each other as a result of the comparison, said comparing means produces an output signal; switching means permitting the output signal of the solid state image pick-up device to pass therethrough in a first switching position, and responding to the output signal from said comparing means to be set to a second switching position, thereby permitting the output signal from the solid state image pick-up device to pass therethrough by way of said delay means; a data generating circuit producing an address data corresponding to the output signal of said control signal generating circuit to the input terminal of said memory means; and a comparing circuit for comparing the output signal of the image pick-up device with a first reference signal, in which, when the output signal of the image pick-up device is larger than the first reference signal, said comparing circuit produces an output signal to cause said memory means to be set in a write-in condition, whereby said comparing circuit sequentially writes address data from said address data generating circuit into said memory means.

Claim 9

A blemish compensating system used for a solid state image pick-up device having a plurality of image pick-up elements which are arranged to store electric charges corresponding to an optical image formed on the light sensitive portions thereof and are sequentially energized by a driving circuit in response to an output signal from a control signal generating means to derive out the electric charges stored on the respective image pick-up elements, comprising: memory means for storing address data representing the position of a defective solid state image pick-up element or elements; delay means for delaying an output signal from said solid state image pick-up device; comparing means for comparing the address data corresponding to the position of that image pick-up element which is energized by said driving circuit to produce an output signal with the address data read out from said memory means, in which, when both the data are coincident with each other as a result of the comparison, said comparing means produces an output signal; switching means permitting the output signal of the solid state image pick-up device to pass therethrough in a first switching position, and responding to the output signal from said comparing means to be set to a second switching position, thereby permitting the output signal from the solid state image pick-up device to pass therethrough by way of said delay means; a data generating circuit producing an address data corresponding to the output signal of said control signal generating circuit to the input terminal of said memory means; and a comparing circuit for comparing the output signal of the image pick-up device with a first reference signal, in which, when the output signal of the image pick-up device is larger than the first reference signal, said comparing circuit produces an output signal to cause said memory means to be set in a write-in condition, whereby said comparing circuit sequentially writes address data from said address data generating circuit into said memory means.

Claim 10

A blemish compensating system used for a solid state image pick-up device having a plurality of image pick-up elements which are arranged to store electric charges corresponding to an optical image formed on the light sensitive portions thereof and are sequentially energized by a driving circuit in response to an output signal from a control signal generating means to derive out the electric charges stored on the respective image pick-up elements, comprising: memory means for storing address data representing the position of a defective solid state image pick-up element or elements; delay means for delaying an output signal from said solid state image pick-up device; comparing means for comparing the address data corresponding to the position of that image pick-up element which is energized by said driving circuit to produce an output signal with the address data read out from said memory means, in which, when both the data are coincident with each other as a result of the comparison, said comparing means produces an output signal; switching means permitting the output signal of the solid state image pick-up device to pass therethrough in a first switching position, and responding to the output signal from said comparing means to be set to a second switching position, thereby permitting the output signal from the solid state image pick-up device to pass therethrough by way of said delay means; a data generating circuit producing an address data corresponding to the output signal of said control signal generating circuit to the input terminal of said memory means; and a comparing circuit for comparing the output signal of the image pick-up device with a first reference signal, in which, when the output signal of the image pick-up device is smaller than the first reference signal, said comparing circuit produces an output signal to cause said memory means to be set in a write-in condition, whereby said comparing circuit sequentially writes address data from said address data generating circuit into said memory means.

Claim 11

A blemish compensating system used for a solid state image pick-up device having a plurality of image pick-up elements which are arranged to store electric charges corresponding to an optical image formed on the light sensitive portions thereof and are sequentially energized by a driving circuit in response to an output signal from a control signal generating means to derive out the electric charges stored on the respective image pick-up elements, comprising: memory means for storing address data representing the position of a defective solid state image pick-up element or elements; delay means for delaying an output signal from said solid state image pick-up device; comparing means for comparing the address data corresponding to the position of that image pick-up element which is energized by said driving circuit to produce an output signal with the address data read out from said memory means, in which, when both the data are coincident with each other as a result of the comparison, said comparing means produces an output signal; switching means permitting the output signal of the solid state image pick-up device to pass therethrough in a first switching position, and responding to the output signal from said comparing means to be set to a second switching position, thereby permitting the output signal from the solid state image pick-up device to pass therethrough by way of said delay means; a data generating circuit producing an address data corresponding to the output signal of said control signal generating circuit to the input terminal of said memory means; and a comparing circuit for comparing the output signal of the image pick-up device with a first reference signal, in which, when the output signal of the image pick-up device is smaller than the first reference signal, said comparing circuit produces an output signal to cause said memory means to be set in a write-in condition, whereby said comparing circuit sequentially writes address data from said address data generating circuit into said memory means.