Patent US4234803A successfully refreshed from Google Patents.
US4234803A
Expired / Lapsed
US
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Integrated logic circuit arrangement
Assignee: Nippon Gakki Co Ltd
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Filing: 1978-04-24
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Granted: 1980-11-18
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Expires: 1998-04-24
Abstract
Abstract An integrated logic circuit arrangement comprising: an input junction field effect transistor having at least one source for receiving a digital input signal, a drain to which a load is connected, and gate held at a reference potential, said junction field effect transistor being operative to effect switching operation in accordance with said digital input signal; and an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain. This integrated logic circuit arrangement provides high speed logic operation, low power dissipation and high integration density.
Inventors
- 👤 Terumoto Nonaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 08:50
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09403; H03K19/09418; H10; H10D; H10D84/00; H10D84/40; H10D84/401
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
165 words
An integrated logic circuit arrangement comprising: an input junction field effect transistor having at least one source for receiving a digital input signal, a drain to which a load is connected, and a gate held at a fixed DC reference potential, said junction field effect transistor being operative to effect switching operation in accordance with said digital input signal, said load being adapted for connection between said drain and a power source; an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain; said output bipolar type transistor having a load connected to the emitter of said output bipolar transistor, whereby said output bipolar transistor behaves as an emitter-follower transistor; and a second emitter-follower transistor, the emitter of said output bipolar type transistor serving as the first mentioned emitter-follower transistor being connected to an emitter output terminal of said second emitter-follower transistor to thereby form a wired OR logic circuit.
Claim 2
Dependent Claim
165 words
An integrated logic circuit arrangement comprising: an input junction field effect transistor having at least one source for receiving a digital input signal, a drain to which a load is connected, and a gate held at a fixed DC reference potential, said junction field effect transistor being operative to effect switching operation in accordance with said digital input signal, said load being adapted for connection between said drain and a power source; an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain; said output bipolar type transistor having a load connected to the emitter of said output bipolar transistor, whereby said output bipolar transistor behaves as an emitter-follower transistor; and a second emitter-follower transistor, the emitter of said output bipolar type transistor serving as the first mentioned emitter-follower transistor being connected to an emitter output terminal of said second emitter-follower transistor to thereby form a wired OR logic circuit.
Claim 3
Dependent Claim
142 words
An integrated logic circuit comprising: an input junction field effect transistor having at least one source for receiving a digital input signal, a drain to which a load is connected, and a gate, held at a reference potential, said junction field effect transistor being operative to effect switching operation in accordance with said digital input signal said load being connected between said drain and a power source; and an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain, the emitter of said output bipolar type transistor having a load connected thereto whereby said output bipolar transistor behaves as an emitter-follower transistor, wherein further the emitter of said output bipolar transistor is connected to an output terminal of another emitter-follower transistor to form a wired OR logic.
Claim 4
Dependent Claim
142 words
An integrated logic circuit comprising: an input junction field effect transistor having at least one source for receiving a digital input signal, a drain to which a load is connected, and a gate, held at a reference potential, said junction field effect transistor being operative to effect switching operation in accordance with said digital input signal said load being connected between said drain and a power source; and an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain, the emitter of said output bipolar type transistor having a load connected thereto whereby said output bipolar transistor behaves as an emitter-follower transistor, wherein further the emitter of said output bipolar transistor is connected to an output terminal of another emitter-follower transistor to form a wired OR logic.
Claim 5
Dependent Claim
91 words
An integrated logic circuit comprising: an input junction field effect transistor having a plurality of sources, each receiving a respective digital input signal, a drain having a load connected thereto, and a gate held at a reference potential, said plural source junction field effect transistor being operative to effect switching operation in accordance with said digital input signal and an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain, whereby an AND logic is formed.
Claim 6
Dependent Claim
91 words
An integrated logic circuit comprising: an input junction field effect transistor having a plurality of sources, each receiving a respective digital input signal, a drain having a load connected thereto, and a gate held at a reference potential, said plural source junction field effect transistor being operative to effect switching operation in accordance with said digital input signal and an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain, whereby an AND logic is formed.
Claim 7
Dependent Claim
34 words
An integrated logic circuit arrangement according to claim 3, in which: said output bipolar type transistor has a load connected to the emitter thereof, whereby said output bipolar transistor operates as an emitter-follower transistor.
Claim 8
Dependent Claim
40 words
An integrated logic circuit arrangement according to claim 4, in which: the emitter of said output bipolar type transistor serving as the emitter-follower transistor is connected to an output terminal of another emitter-follower circuit, thereby forming a wired OR logic.
Claim 9
Dependent Claim
36 words
An integrated logic circuit arrangement according to claim 3, in which: the collector of said output bipolar type transistor has its collector connected to a load, so that this transistor serves to operate as an inverter.
Claim 10
Dependent Claim
17 words
The integrated logic circuit of claim 3 wherein output bipolar type transistor includes a plurality of emitters.
Claim 11
Dependent Claim
92 words
An integrated logic circuit arrangement comprising: an input junction field effect transistor having a plurality of sources for receiving digital input signals, a drain to which a load is connected, and a gate held at a fixed DC reference potential, said junction field effect transistor being operative to effect switching operation in accordance with said digital input signal, said plural sources forming an AND logic; and an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain.
Claim 12
Dependent Claim
92 words
An integrated logic circuit arrangement comprising: an input junction field effect transistor having a plurality of sources for receiving digital input signals, a drain to which a load is connected, and a gate held at a fixed DC reference potential, said junction field effect transistor being operative to effect switching operation in accordance with said digital input signal, said plural sources forming an AND logic; and an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain.
Claim 13
Dependent Claim
38 words
An integrated logic circuit arrangement according to claim 8, in which: said output bipolar type transistor has a load connected to the emitter of said output bipolar transistor, whereby said output bipolar transistor behaves as an emitter-follower transistor.
Claim 14
Dependent Claim
49 words
An integrated logic circuit arrangement according to claim 9, further comprising a second emitter-follower transistor in which: the emitter of said output bipolar type transistor serving as the first mentioned emitter-follower transistor is connected to an output terminal of said second emitter-follower transistor thereby forming a wired OR logic.
Claim 15
Dependent Claim
36 words
An integrated logic circuit arrangement according to claim 8, in which: the collector of said output bipolar type transistor is connected to a load, so that said output bipolar transistor serves to operate as an inverter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-11-18 | 1984-05-19 | 1984-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-11-18 | 1988-05-19 | 1988-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-11-18 | 1992-05-19 | 1992-11-18 | $7700.00 | Window Closed / Lapsed |