Digital signal selective circuit

Claim 2

A digital signal selective circuit responsive to a periodic input signal having an operating characteristic occurring at a desired regular periodic interval for a desired length of time, comprising: clock signal generating means for providing reference clock pulses; first counting means for counting said reference clock pulses and for registering a resulting count therein which provides a measurement of the length of time since the last occurrence of said operating characteristic; means for providing an output pulse in response to said operating characteristic occurring at a time when said count in said first counting means is within a predetermined range, said means for providing an output pulse including bistable circuit means providing a predetermined signal level whenever the count in said first counting means is within said predetermined range, and logic circuit means providing an output pulse in response to the simultaneous occurrence of said predetermined signal level and said operating characteristic; and second counting means for counting each said output pulse and providing an output signal when said second counting means attains a predetermined count.

Claim 3

A digital signal selective circuit according to claim 1; wherein said periodic input signal oscillates between positive and negative portions with respect to a reference level, and said operating characteristic is the transition from one to the other of said positive and negative portions.

Claim 4

A digital signal selective circuit according to claim 1; further comprising delay means responsive to said output signal for providing a signal at a time delayed by a predetermined amount after said second counting means attains said predetermined count.

Claim 5

A digital signal selective circuit for responding to a periodic input signal whenever the latter has a frequency within a predetermined range of frequencies for a predetermined length of time, comprising: input means receiving said input signal; clock means providing clocking pulses at a frequency substantially greater than the highest frequency in said predetermined range; counting means for counting said clocking pulses and providing an output after attaining a specified count thereof, said counting means including first and second counters each having an input terminal, an output terminal, a reset terminal and a gating terminal, said clocking pulses being applied to the input terminal of said first counter, and counting pulse generator means connected with said input means and being interposed between the output terminal of said first counter and the input terminal of said second counter for providing a counting pulse to said second counter for each cycle of said periodic input signal whenever the frequency of said input signal is within said predetermined range; the output terminal of said second counter providing said output of the counting means after attaining said specified count; gating means responsive to said input signal for enabling said counting means whenever said input is present at said input means, said gating means being connected with the gating terminals of said first and second counters; reset means connected with said counting means and responsive to said input signal for resetting said counting means whenever the frequency of said input signal is outside said predetermined range, thereby preventing said counting means from attaining said specified count when said frequency is outside said range, said reset means being connected with said reset terminals of said first and second counters; and output means responsive to said output of the counting means for providing an output signal.

Claim 6

A digital signal selective circuit for responding to a periodic input signal whenever the latter has a frequency within a predetermined range of frequencies for a predetermined length of time, comprising: input means receiving said input signal; clock means providing clocking pulses at a frequency substantially greater than the highest frequency in said predetermined range; counting means for counting said clocking pulses and providing an output after attaining a specified count thereof, said counting means including first and second counters each having an input terminal, an output terminal, a reset terminal and a gating terminal, said clocking pulses being applied to the input terminal of said first counter, and counting pulse generator means connected with said input means and being interposed between the output terminal of said first counter and the input terminal of said second counter for providing a counting pulse to said second counter for each cycle of said periodic input signal whenever the frequency of said input signal is within said predetermined range; the output terminal of said second counter providing said output of the counting means after attaining said specified count; gating means responsive to said input signal for enabling said counting means whenever said input is present at said input means, said gating means being connected with the gating terminals of said first and second counters; reset means connected with said counting means and responsive to said input signal for resetting said counting means whenever the frequency of said input signal is outside said predetermined range, thereby preventing said counting means from attaining said specified count when said frequency is outside said range, said reset means being connected with said reset terminals of said first and second counters; and output means responsive to said output of the counting means for providing an output signal.

Claim 7

A digital signal selective circuit for responsing to a periodic input signal whenever the latter has a frequency within a predetermined range of frequencies for a predetermined length of time, comprising: input means receiving said input signal; clock means providing clocking pulses at a frequency substantially greater than the highest frequency in said predetermined range; counting means for counting said clocking pulses and providing an output after attaining a specified count thereof; gating means responsive to said input signal for enabling said counting means whenever said input is present at said input means; output means responsive to said output of the counting means for providing an output signal, said output means including delay circuit means providing said output signal a specified time after said counting means attains said specified count; and reset means connected with said counting means and responsive to said input signal for resetting said counting means whenever the frequency of said input signal is outside said predetermined range thereby preventing said counting means from attaining said specified count when said frequency is outside said range, said reset means being connected with said delay circuit means for resetting said counting means said specified time after said counting means attains said specified count.

Claim 8

A digital signal selective circuit for responsing to a periodic input signal whenever the latter has a frequency within a predetermined range of frequencies for a predetermined length of time, comprising: input means receiving said input signal; clock means providing clocking pulses at a frequency substantially greater than the highest frequency in said predetermined range; counting means for counting said clocking pulses and providing an output after attaining a specified count thereof; gating means responsive to said input signal for enabling said counting means whenever said input is present at said input means; output means responsive to said output of the counting means for providing an output signal, said output means including delay circuit means providing said output signal a specified time after said counting means attains said specified count; and reset means connected with said counting means and responsive to said input signal for resetting said counting means whenever the frequency of said input signal is outside said predetermined range thereby preventing said counting means from attaining said specified count when said frequency is outside said range, said reset means being connected with said delay circuit means for resetting said counting means said specified time after said counting means attains said specified count.

Claim 9

A digital signal selective circuit for responding to a periodic input signal whenever the latter has a frequency within a predetermined range of frequencies for a predetermined length of time, comprising input means receiving said input signal; first pulse generating means connected with said input means and providing a first pulse at the beginning of each period during which the input signal has a frequency within said predetermined range; second pulse generating means connected with said input means providing second pulses approximately at the frequency of said input signal; clock generator means providing clock pulses at a frequency substantially greater than the highest frequency of said predetermined range; a first counter having an input terminal receiving said clock pulses, and output terminal, a gate terminal, and a reset terminal; counting pulse generator means connected with the output terminal of said first counter and with said second pulse generator means for providing a counting pulse whenever one of said second pulses occurs at a time when said first counter has attained a count between first and second predetermined counts; a second counter having an input terminal receiving each said counting pulse, an output terminal, a gate terminal, and a reset terminal; gate signal generator means connected with said first pulse generating means and with said counting pulse generator means for providing a gating signal to the gate terminals of said first and second counters, said gate signal generator means providing said gating signal with a first value for a predetermined period in response to the occurrence of any one of said first pulse and said counting pulse, and said gating signal generator means providing said gating signal with a second value when both said first pulse and said counting pulse are absent for a length of time at least equal to said predetermined period; reset means for providing a reset signal to the reset terminals of said first and second counters in response to a transition of said gating signal between said first and second values; and output means connected with the output terminal of said second counter for providing said output signal whenever said second counter attains a predetermined count.

Claim 10

A digital signal selective circuit for responding to a periodic input signal whenever the latter has a frequency within a predetermined range of frequencies for a predetermined length of time, comprising input means receiving said input signal; first pulse generating means connected with said input means and providing a first pulse at the beginning of each period during which the input signal has a frequency within said predetermined range; second pulse generating means connected with said input means providing second pulses approximately at the frequency of said input signal; clock generator means providing clock pulses at a frequency substantially greater than the highest frequency of said predetermined range; a first counter having an input terminal receiving said clock pulses, and output terminal, a gate terminal, and a reset terminal; counting pulse generator means connected with the output terminal of said first counter and with said second pulse generator means for providing a counting pulse whenever one of said second pulses occurs at a time when said first counter has attained a count between first and second predetermined counts; a second counter having an input terminal receiving each said counting pulse, an output terminal, a gate terminal, and a reset terminal; gate signal generator means connected with said first pulse generating means and with said counting pulse generator means for providing a gating signal to the gate terminals of said first and second counters, said gate signal generator means providing said gating signal with a first value for a predetermined period in response to the occurrence of any one of said first pulse and said counting pulse, and said gating signal generator means providing said gating signal with a second value when both said first pulse and said counting pulse are absent for a length of time at least equal to said predetermined period; reset means for providing a reset signal to the reset terminals of said first and second counters in response to a transition of said gating signal between said first and second values; and output means connected with the output terminal of said second counter for providing said output signal whenever said second counter attains a predetermined count.

Claim 11

A digital signal selective circuit according to claim 6; wherein said input means includes waveshaping means receiving the input signal for producing a shaped signal of predetermined amplitude and having the frequency of said periodic input signal, said shaped signal being applied to said first and second pulse generating means.

Claim 12

A digital signal selective circuit according to claim 7; wherein said waveshaping means includes a Schmitt trigger.

Claim 13

A digital signal selective circuit according to claim 6; wherein said second pulse generating means includes means for synchronizing said second pulses with said clock pulses.

Claim 14

A digital signal selective circuit according to claim 6; wherein said second pulse generating means comprises a first bistable circuit having input terminals connected to said input means, an output terminal, and an inverse output terminal, and a pulse generator providing said second pulses in response to transitions in level at said output terminal of the bistable circuit.

Claim 15

A digital signal selective circuit according to claim 10; wherein said first pulse generating means includes a second bistable circuit having an input terminal, a clear terminal, and an output terminal, said input terminal being connected to said inverse output terminal of the first bistable circuit, said clear terminal being connected with said reset means to receive said reset signal, and another pulse generator providing each said first pulse in response to a transition in level at said output terminal of said second bistable circuit.

Claim 16

A digital signal selective circuit according to claim 6; wherein said gate signal generator means includes a logic circuit having inputs connected with said first pulse generating means and with said counting pulse generating means, said logic circuit having an output at which a logic signal is provided whenever a pulse appears at one of said inputs thereof, and a monostable multivibrator providing said gating signal of said first value in response to said logic signal.

Claim 17

A digital signal selective circuit according to claim 12; wherein, in the absence of said first pulse and said counting pulses, said gating signal has said first value for a predetermined period exceeding the period of the lowest frequency in said predetermined range.

Claim 18

A digital signal selective circuit according to claim 13; wherein said predetermined period is approximately 3/2 the period of said lowest frequency.

Claim 19

A digital signal selective circuit according to claim 6; wherein said counting pulse generator means includes a bistable circuit having an input terminal, a clear terminal, and an output terminal, said input terminal of the bistable circuit being connected with said first counter and said clear terminal being connected with said first counter so that an output of said bistable circuit appearing at said output terminal shifts from a first level to a second level when said first counter attains said first predetermined count and shifts from said second level back to said first level when said first counter attains said second predetermined count, and a logic circuit connected to said output terminal of said bistable circuit and to said second pulse generating means for providing said counting pulse whenever said second pulse occurs while said output of said bistable circuit is at said second level.

Claim 20

A digital signal selective circuit according to claim 6; wherein said reset means includes a pulse generator connected with said gate signal generator means said said counters and providing said reset signal in response to a transition of said gating signal between said first and second values.

Claim 21

A digital signal selective circuit according to claim 16; wherein said reset means further includes logic OR gates between said pulse generator of said reset means and each of said first and second counters, each of said OR gates having inputs and an output, said reset signal being applied to one input of each said OR gate, the outputs of said OR gates being connected to respective reset terminals of said first and second counters; and a delay circuit connected with the output terminal of said second counter providing a delayed signal delayed by a predetermined amount after said second counter attains said predetermined count, said delayed signal being applied to another input of each of said OR gates.

Claim 22

A digital signal selective circuit according to claim 17; wherein said second pulse generator means is connected to an input of the OR gate having its output connected with said first counter, so that said second pulses are applied to said input of said OR gate having its output connected with said first counter.

Claim 23

A digital signal selective circuit according to claim 6; wherein said output means includes a delay circuit connected with said second counter for providing a delayed signal a predetermined time after said second counter attains said predetermined count.

Claim 24

A digital signal selective circuit according to claim 19; wherein said output means further includes a pulse generator connected with said delay circuit for providing an output pulse in response to said delayed signal.