Patent US4231108A successfully refreshed from Google Patents.
US4231108A
Expired / Lapsed
US
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Semiconductor integrated circuit device
Assignee: Fujitsu Ltd
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Filing: 1979-06-13
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Granted: 1980-10-28
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Expires: 1999-06-13
Abstract
Abstract An improved semiconductor integrated circuit device having a memory cell array formed of integrated injection logic memory cells. The semiconductor integrated circuit according to the present invention includes integration injection logic memory cells which are arranged in matrix form, word lines and bit lines which are connected to the memory cells arranged in the row or column directions, one of the word lines being formed by a semiconductor bulk, current sources provided at least at both ends of the word lines or the bit lines.
Inventors
- 👤 Masao Suzuki
- 👤 Toshio Hayashi
- 👤 Kuniyasu Kawarada
- 👤 Kazuhiro Toyoda
- 👤 Chikai Ono
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:01
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; G11C5/063; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; G11C11/413; G11C11/414; G11C11/415; H; H10; H10B; H10B10/00; H10B10/10
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
179 words
A semiconductor integrated circuit device having an array of integrated injection logic memory cells, each said integrated injection logic memory cell comprising a pair of first and second transistors of first conduction type with common emitters forming an injector connected to a first word line, a pair of third and fourth transistors of second conduction type having their collectors connected to the collectors of said first and second transistors, respectively, the base of said third transistor being connected to said collector of said fourth transistor and the base of said fourth transistor being connected to said collector of said third transistor, said first and second transistors having bases connected in common to emitters of said third and fourth transistors and to a second word line, said second word line thusly connecting to each said memory cell of said at least one array, said semiconductor integrated circuit device comprising a bulk of said semiconductor device forming said second word line, at least two current sources connected in a distributed fashion to said second word line of said memory cell array.
Claim 2
Dependent Claim
179 words
A semiconductor integrated circuit device having an array of integrated injection logic memory cells, each said integrated injection logic memory cell comprising a pair of first and second transistors of first conduction type with common emitters forming an injector connected to a first word line, a pair of third and fourth transistors of second conduction type having their collectors connected to the collectors of said first and second transistors, respectively, the base of said third transistor being connected to said collector of said fourth transistor and the base of said fourth transistor being connected to said collector of said third transistor, said first and second transistors having bases connected in common to emitters of said third and fourth transistors and to a second word line, said second word line thusly connecting to each said memory cell of said at least one array, said semiconductor integrated circuit device comprising a bulk of said semiconductor device forming said second word line, at least two current sources connected in a distributed fashion to said second word line of said memory cell array.
Claim 3
Dependent Claim
75 words
A semiconductor integrated circuit device according to claim 1 and further having first and second bit lines, each said integrated injection logic memory cell further comprising a pair of fifth and sixth transistors of second conduction type having bases respectively connected to said bases of said third and fourth transistors and collectors connected to said second word line, and said fifth and sixth transistors having emitters respectively connected to said first and second bit lines.
Claim 4
Dependent Claim
37 words
A semiconductor integrated circuit device according to claim 1, said at least one memory array further comprising at least one current source connected at a middle portion of said second word line of said memory cell array.
Claim 5
Dependent Claim
45 words
A semiconductor integrated circuit device according to claim 1, wherein at least one of said current sources comprises a transistor with its collector connected to said second word line, its emitter connected to a potential source, and its base connected to a bias voltage source.
Claim 6
Dependent Claim
14 words
A semiconductor circuit device according to claim 4, wherein each has the same area.
Claim 7
Dependent Claim
71 words
A semiconductor integrated circuit device according to claim 3, each said current source comprising a transistor with its collector connected to said memory array, its emitter connected to a potential source, and its base connected to a bias voltage source, wherein the distribution of the injection current of said injector of each said memory cell is adjusted by changing the ratio of emitter areas of said transistors of said current sources.
Claim 8
Dependent Claim
45 words
A semiconductor integrated circuit device according to claim 6, wherein the emitter area of the transistor of the current source at the middle portion of said memory array is twice that of the transistors of said current sources at each end of said memory array.
Claim 9
Dependent Claim
20 words
The device of claim 1 comprising at least one of said current sources at each of said second word line.
Claim 10
Dependent Claim
58 words
The device of claim 1, 3, 5, 7 or 8, each said memory cell of said at least one array having a corresponding write threshold current and write pulse width, and said current sources of said array comprising means for equalizing said write threshold current and write pulse widths of the cells of said at least one array.
References Cited (Backward Citations)
US3959781A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-10-28 | 1984-04-28 | 1984-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-10-28 | 1988-04-28 | 1988-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-10-28 | 1992-04-28 | 1992-10-28 | $7700.00 | Window Closed / Lapsed |