Bias circuit

Claim 2

A bias circuit, having a d.c. supply terminal, a bias output terminal, and a reference potential terminal, comprising: first and second elements arranged in series between the bias output terminal and the reference potential terminal of said bias circuit, said first and second elements generating a voltage between the bias output terminal and the reference potential terminal, said voltage being equal to the sum of two voltage drops in a forward p-n junction; first and second transistors connected in series, the collectors of said first and second transistors being connected at a node, each of said first and second transistors having a base which is connected to a terminal between said first and second elements, wherein said first and second transistors generate a difference current at said node equal to the difference between the collector currents of said first and second transistors; resistor means, operatively connected to said second element, for determining the value of a constant current for generating bias voltages; a third transistor arranged between the bias output terminal and the d.c. supply terminal; a negative feedback circuit arranged between the base of said third transistor and said node, said difference current being introduced as an input thereto; a starting element, connected to the d.c. supply terminal, for supplying currents to said first and second elements and to said first and second transistors in an initial state when the power is turned on, whereby said negative feedback circuit operates to generate said constant current.

Claim 3

A bias circuit as set forth in claim 1, wherein said resistor means comprises a first resistor connected between said first and second elements and a secnod resistor operatively connected to said second transistor.

Claim 4

A bias circuit as set forth in claim 1, wherein said resistor means comprises of a single resistor connected to said second element.

Claim 5

A bias circuit as set forth in claim 1, wherein said bias circuit further comprises a fourth transistor whose base and emitter are connected to the base and the emitter of said third transistor, respectively, whereby a collector current of said fourth transistor may be obtained as a bias current.

Claim 6

A bias circuit as set forth in claim 1, further comprising at least one diode arranged between said first and second elements, whereby a plurality of bias voltages may be output from the terminals of said at least one diode.

Claim 7

A bias circuit as set forth in claim 5, wherein said at least one diode is a base-collector connected transistor.

Claim 8

A bias circuit as set forth in claim 1, wherein each of said first and second elements is a transistor.

Claim 9

A bias circuit as set forth in claim 1, wherein said starting element is a resistor.

Claim 10

A bias circuit, having a voltage supply terminal, a ground terminal, and an output terminal, comprising: a first transistor, having a collector, emitter and base, said first transistor emitter operatively connected to the voltage supply terminal and said first transistor collector operatively connected to the output terminal; a first resistor operatively connected between the voltage supply terminal and the output terminal; a second transistor, having a collector, emitter and base, said second transistor collector operatively connected to said first transistor base; a second resistor operatively connected to said second transistor emitter and to the ground terminal; a first capacitor operatively connected to said second transistor base and to the ground terminal; a third transistor, having a collector, emitter and base, said third transistor emitter operatively connected to the output terminal and said third transistor base operatively connected to said third transistor collector; a fourth transistor, having a collector, emitter and base, said fourth transistor emitter operatively connected to the output terminal, said fourth transistor base operatively connected to said third transistor collector and said third transistor base, and said fourth transistor collector operatively connected to said second transistor base and said first capacitor; a fifth transistor, having a collector, emitter and base, said fifth transistor base and collector operatively connected to said third transistor base, said fifth transistor emitter operatively connected to the ground terminal; a sixth transistor, having a collector, emitter and base, said sixth transistor collector operatively connected to said fourth transistor collector, said second transistor base, and said first capacitor, said sixth transistor base operatively connected to said fifth transistor base and collector, said sixth transistor emitter operatively connected to the ground terminal; and a seventh transistor, having a collector, emitter and base, said seventh transistor emitter operatively connected to the voltage supply terminal, said seventh transistor base operatively connected to said first transistor base and said second transistor collector.

Claim 11

A bias circuit, having a voltage supply terminal, a ground terminal, and an output terminal, comprising: a first transistor, having a collector, emitter and base, said first transistor emitter operatively connected to the voltage supply terminal and said first transistor collector operatively connected to the output terminal; a first resistor operatively connected between the voltage supply terminal and the output terminal; a second transistor, having a collector, emitter and base, said second transistor collector operatively connected to said first transistor base; a second resistor operatively connected to said second transistor emitter and to the ground terminal; a first capacitor operatively connected to said second transistor base and to the ground terminal; a third transistor, having a collector, emitter and base, said third transistor emitter operatively connected to the output terminal and said third transistor base operatively connected to said third transistor collector; a fourth transistor, having a collector, emitter and base, said fourth transistor emitter operatively connected to the output terminal, said fourth transistor base operatively connected to said third transistor collector and said third transistor base, and said fourth transistor collector operatively connected to said second transistor base and said first capacitor; a fifth transistor, having a collector, emitter and base, said fifth transistor base and collector operatively connected to said third transistor base, said fifth transistor emitter operatively connected to the ground terminal; a sixth transistor, having a collector, emitter and base, said sixth transistor collector operatively connected to said fourth transistor collector, said second transistor base, and said first capacitor, said sixth transistor base operatively connected to said fifth transistor base and collector, said sixth transistor emitter operatively connected to the ground terminal; and a seventh transistor, having a collector, emitter and base, said seventh transistor emitter operatively connected to the voltage supply terminal, said seventh transistor base operatively connected to said first transistor base and said second transistor collector.

Claim 12

The bias circuit as set forth in claim 9, further comprising: a third resistor operatively connected between said third transistor collector and base; and a fourth resistor operatively connected between said sixth transistor emitter and the ground terminal.

Claim 13

The bias circuit as set forth in claim 10, further comprising at least one diode operatively connected between said third resistor and said fifth transistor collector.

Claim 14

The bias circuit as set forth in claim 9, further comprising a third resistor operatively connected between said fifth transistor emitter and the ground terminal.